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Merge 6b5fbe37f0 into 012ddc2f1e

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Martin Povišer 2025-09-08 10:10:29 +12:00 • committed by GitHub
commit b5110fc69c
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1 changed files with 13 additions and 9 deletions
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22
passes/sat/sim.cc
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@ -301,16 +301,18 @@ struct SimInstance
if (mod != nullptr) {
dirty_children.insert(new SimInstance(shared, scope + "." + RTLIL::unescape_id(cell->name), mod, cell, this));
}
for (auto &port : cell->connections()) {
} else {
for (auto &port : cell->connections())
if (cell->input(port.first))
for (auto bit : sigmap(port.second)) {
upd_cells[bit].insert(cell);
// Make sure cell inputs connected to constants are updated in the first cycle
if (bit.wire == nullptr)
dirty_bits.insert(bit);
}
for (auto bit : sigmap(port.second))
upd_cells[bit].insert(cell);
// Update all cells in the first cycle (to propagate constants but also to
// handle edge cases in which cells have defined output values in presence of
// undefined inputs). This is with the exception of few cells which don't have
// any inputs and should never be queued up for updating.
if (!cell->type.in(ID($initstate), ID($anyconst), ID($anyseq), ID($allconst), ID($allseq)))
dirty_cells.insert(cell);
}
if (RTLIL::builtin_ff_cell_types().count(cell->type) || cell->type == ID($anyinit)) {
@ -507,6 +509,8 @@ struct SimInstance
void update_cell(Cell *cell)
{
log_assert(!cell->type.in(ID($initstate), ID($anyconst), ID($anyseq), ID($allconst), ID($allseq)));
if (ff_database.count(cell))
return;