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Add FFs and related tests

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Lofty 2024-03-01 10:55:54 +01:00 committed by Miodrag Milanovic
parent b4a17cccc3
commit b4e9bb0d85
7 changed files with 187 additions and 0 deletions

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read_verilog ../common/adffs.v
design -save read
hierarchy -top adff
proc
equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adff # Constrain all select calls below inside the top module
select -assert-count 1 t:NX_DFF
select -assert-none t:NX_DFF %% t:* %D
design -load read
hierarchy -top adffn
proc
equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adffn # Constrain all select calls below inside the top module
select -assert-count 1 t:NX_DFF
select -assert-count 1 t:NX_LUT
select -assert-none t:NX_DFF t:NX_LUT %% t:* %D
design -load read
hierarchy -top dffs
proc
equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffs # Constrain all select calls below inside the top module
select -assert-count 1 t:NX_DFF
select -assert-none t:NX_DFF %% t:* %D
design -load read
hierarchy -top ndffnr
proc
equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd ndffnr # Constrain all select calls below inside the top module
select -assert-count 1 t:NX_DFF
select -assert-count 1 t:NX_LUT
select -assert-none t:NX_DFF t:NX_LUT %% t:* %D