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Add FFs and related tests
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@ -33,3 +33,36 @@ module \$lut (A, Y);
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end
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endgenerate
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endmodule
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(* techmap_celltype = "$_DFF_[NP]P[01]_" *)
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module dff(input D, C, R, output Q);
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parameter _TECHMAP_CELLTYPE = "$_DFF_PP1_";
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localparam dff_edge = _TECHMAP_CELLTYPE[6*8 +: 8] == "N";
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localparam dff_type = _TECHMAP_CELLTYPE[8*8 +: 8] == "1";
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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NX_DFF #(.dff_ctxt(1'b0), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b0), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q));
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endmodule
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(* techmap_celltype = "$_ALDFF_[NP]P_" *)
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module aldff(input D, C, L, AD, output Q);
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parameter _TECHMAP_CELLTYPE = "$_ALDFF_PP_";
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localparam dff_edge = _TECHMAP_CELLTYPE[8*8 +: 8] == "N";
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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NX_DFF #(.dff_ctxt(1'b0), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(2)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(AD), .R(L), .O(Q));
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endmodule
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module \$_SDFF_PP0_ (input D, C, R, output Q);
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NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b0), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q));
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endmodule
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module \$_SDFF_PP1_ (input D, C, R, output Q);
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NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b0), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(1'b1)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q));
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endmodule
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module \$_SDFF_NP0_ (input D, C, R, output Q);
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NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b1), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q));
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endmodule
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module \$_SDFF_NP1_ (input D, C, R, output Q);
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NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b1), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(1'b1)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q));
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endmodule
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@ -8,3 +8,28 @@ wire [1:0] s3 = I2 ? s2[3:2] : s2[1:0];
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assign O = I1 ? s3[1] : s3[0];
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endmodule
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module NX_DFF(input I, CK, L, R, output reg O);
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parameter dff_ctxt = 1'bx;
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parameter dff_edge = 1'b0;
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parameter dff_init = 1'b0;
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parameter dff_load = 1'b0;
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parameter dff_sync = 1'b0;
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parameter dff_type = 1'b0;
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initial begin
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O = dff_ctxt;
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end
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wire clock = CK ^ dff_edge;
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wire load = (dff_type == 2) ? (dff_load ? L : 1'bx) : dff_type;
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wire async_reset = !dff_sync && dff_init && R;
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wire sync_reset = dff_sync && dff_init && R;
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always @(posedge clock, posedge async_reset)
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if (async_reset) O <= load;
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else if (sync_reset) O <= load;
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else O <= I;
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endmodule
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