From b4dfc2e2d098835c8b6c1dd6829fd29ffe6d87de Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Thu, 6 Mar 2025 17:59:46 +0100
Subject: [PATCH] quicklogic: rename dspv1 full synth_quicklogic test for
 clarity

---
 tests/arch/quicklogic/qlf_k6n10f/{dsp.ys => dspv1_full.ys} | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)
 rename tests/arch/quicklogic/qlf_k6n10f/{dsp.ys => dspv1_full.ys} (93%)

diff --git a/tests/arch/quicklogic/qlf_k6n10f/dsp.ys b/tests/arch/quicklogic/qlf_k6n10f/dspv1_full.ys
similarity index 93%
rename from tests/arch/quicklogic/qlf_k6n10f/dsp.ys
rename to tests/arch/quicklogic/qlf_k6n10f/dspv1_full.ys
index 1e652855b..6f61b434b 100644
--- a/tests/arch/quicklogic/qlf_k6n10f/dsp.ys
+++ b/tests/arch/quicklogic/qlf_k6n10f/dspv1_full.ys
@@ -21,7 +21,7 @@ EOF
 design -save ast
 proc
 wreduce
-#equiv_opt -async2sync -map +/quicklogic/qlf_k6n10f/dsp_sim.v synth_quicklogic -family qlf_k6n10f
+#equiv_opt -async2sync -map +/quicklogic/qlf_k6n10f/dspv1_sim.v synth_quicklogic -family qlf_k6n10f
 #design -load postopt
 synth_quicklogic -family qlf_k6n10f
 cd top
@@ -114,8 +114,8 @@ always @(posedge clk) begin
 end
 endmodule
 EOF
-read_verilog +/quicklogic/qlf_k6n10f/dsp_sim.v
+read_verilog +/quicklogic/qlf_k6n10f/dspv1_sim.v
 hierarchy -top testbench
 proc
 async2sync
-sim -assert -q -clock clk -n 20
+sim -q -clock clk -n 20 -assert