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initialized iCE40 brams (mode 0)

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This commit is contained in:
Clifford Wolf 2015-04-25 20:44:51 +02:00
parent 4cc4400514
commit b4d7a590e8
5 changed files with 261 additions and 54 deletions
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8
techlibs/ice40/tests/test_bram_tb.v
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@ -1,5 +1,6 @@
module bram_tb #(
parameter ABITS = 8, DBITS = 8
parameter ABITS = 8, DBITS = 8,
parameter INIT_ADDR = 0, INIT_DATA = 0
);
reg clk;
reg [ABITS-1:0] WR_ADDR;
@ -63,6 +64,9 @@ module bram_tb #(
// $dumpfile("testbench.vcd");
// $dumpvars(0, bram_tb);
if (INIT_ADDR || INIT_DATA)
memory[INIT_ADDR] <= INIT_DATA;
xorshift64_next;
xorshift64_next;
xorshift64_next;
@ -85,7 +89,7 @@ module bram_tb #(
WR_ADDR = getaddr(i < 256 ? i[7:4] : xorshift64_state[63:60]);
xorshift64_next;
RD_ADDR = getaddr(i < 256 ? i[3:0] : xorshift64_state[59:56]);
RD_ADDR = i == 0 ? INIT_ADDR : getaddr(i < 256 ? i[3:0] : xorshift64_state[59:56]);
WR_EN = xorshift64_state[55] && ((WR_ADDR & 'hff) != (RD_ADDR & 'hff));
xorshift64_next;