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initialized iCE40 brams (mode 0)

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This commit is contained in:
Clifford Wolf 2015-04-25 20:44:51 +02:00
parent 4cc4400514
commit b4d7a590e8
5 changed files with 261 additions and 54 deletions
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8
techlibs/ice40/tests/test_bram.v
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@ -1,5 +1,6 @@
module bram #(
parameter ABITS = 8, DBITS = 8
parameter ABITS = 8, DBITS = 8,
parameter INIT_ADDR = 0, INIT_DATA = 0
) (
input clk,
@ -12,6 +13,11 @@ module bram #(
);
reg [DBITS-1:0] memory [0:2**ABITS-1];
initial begin
if (INIT_ADDR || INIT_DATA)
memory[INIT_ADDR] <= INIT_DATA;
end
always @(posedge clk) begin
if (WR_EN) memory[WR_ADDR] <= WR_DATA;
RD_DATA <= memory[RD_ADDR];