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initialized iCE40 brams (mode 0)

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This commit is contained in:
Clifford Wolf 2015-04-25 20:44:51 +02:00
parent 4cc4400514
commit b4d7a590e8
5 changed files with 261 additions and 54 deletions
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11
techlibs/ice40/tests/test_bram.sh
View file

@ -5,8 +5,15 @@ set -ex
for abits in 7 8 9 10 11 12; do
for dbits in 2 4 8 16 24 32; do
id="test_bram_${abits}_${dbits}"
sed -e "s/ABITS = ./ABITS = $abits/g; s/DBITS = ./DBITS = $dbits/g;" < test_bram.v > ${id}.v
sed -e "s/ABITS = ./ABITS = $abits/g; s/DBITS = ./DBITS = $dbits/g;" < test_bram_tb.v > ${id}_tb.v
if [ $((RANDOM % 2)) -eq 0 ]; then
iadr=0
idat=0
else
iadr=$((RANDOM % (1 << abits)))
idat=$((RANDOM % (1 << dbits)))
fi
sed -re "s/(ABITS = )0/\1$abits/g; s/(DBITS = )0/\1$dbits/g; s/(INIT_ADDR = )0/\1$iadr/g; s/(INIT_DATA = )0/\1$idat/g;" < test_bram.v > ${id}.v
sed -re "s/(ABITS = )0/\1$abits/g; s/(DBITS = )0/\1$dbits/g; s/(INIT_ADDR = )0/\1$iadr/g; s/(INIT_DATA = )0/\1$idat/g;" < test_bram_tb.v > ${id}_tb.v
../../../yosys -ql ${id}_syn.log -p "synth_ice40" -o ${id}_syn.v ${id}.v
# iverilog -s bram_tb -o ${id}_tb ${id}_syn.v ${id}_tb.v /opt/lscc/iCEcube2.2014.08/verilog/sb_ice_syn.v
iverilog -s bram_tb -o ${id}_tb ${id}_syn.v ${id}_tb.v ../cells_sim.v

8
techlibs/ice40/tests/test_bram.v
View file

@ -1,5 +1,6 @@
module bram #(
parameter ABITS = 8, DBITS = 8
parameter ABITS = 8, DBITS = 8,
parameter INIT_ADDR = 0, INIT_DATA = 0
) (
input clk,
@ -12,6 +13,11 @@ module bram #(
);
reg [DBITS-1:0] memory [0:2**ABITS-1];
initial begin
if (INIT_ADDR || INIT_DATA)
memory[INIT_ADDR] <= INIT_DATA;
end
always @(posedge clk) begin
if (WR_EN) memory[WR_ADDR] <= WR_DATA;
RD_DATA <= memory[RD_ADDR];

8
techlibs/ice40/tests/test_bram_tb.v
View file

@ -1,5 +1,6 @@
module bram_tb #(
parameter ABITS = 8, DBITS = 8
parameter ABITS = 8, DBITS = 8,
parameter INIT_ADDR = 0, INIT_DATA = 0
);
reg clk;
reg [ABITS-1:0] WR_ADDR;
@ -63,6 +64,9 @@ module bram_tb #(
// $dumpfile("testbench.vcd");
// $dumpvars(0, bram_tb);
if (INIT_ADDR || INIT_DATA)
memory[INIT_ADDR] <= INIT_DATA;
xorshift64_next;
xorshift64_next;
xorshift64_next;
@ -85,7 +89,7 @@ module bram_tb #(
WR_ADDR = getaddr(i < 256 ? i[7:4] : xorshift64_state[63:60]);
xorshift64_next;
RD_ADDR = getaddr(i < 256 ? i[3:0] : xorshift64_state[59:56]);
RD_ADDR = i == 0 ? INIT_ADDR : getaddr(i < 256 ? i[3:0] : xorshift64_state[59:56]);
WR_EN = xorshift64_state[55] && ((WR_ADDR & 'hff) != (RD_ADDR & 'hff));
xorshift64_next;