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https://github.com/YosysHQ/yosys
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Added GP_DFFS, GP_DFFR, and GP_DFFSR
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@ -1,20 +1,26 @@
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module \$_DFF_P_ (input D, C, output Q);
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module GP_DFFS(input D, CLK, nSET, output reg Q);
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GP_DFF _TECHMAP_REPLACE_ (
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parameter [0:0] INIT = 1'bx;
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GP_DFFSR #(
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.INIT(INIT),
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.SRMODE(1'b1),
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) _TECHMAP_REPLACE_ (
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.D(D),
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.D(D),
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.Q(Q),
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.CLK(C),
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.CLK(C),
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.nRSTZ(1'b1),
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.nSR(nSET),
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.nSETZ(1'b1)
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.Q(Q)
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);
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);
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endmodule
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endmodule
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module \$_DFFSR_PNN_ (input C, S, R, D, output Q);
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module GP_DFFR(input D, CLK, nRST, output reg Q);
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GP_DFF _TECHMAP_REPLACE_ (
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parameter [0:0] INIT = 1'bx;
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GP_DFFSR #(
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.INIT(INIT),
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.SRMODE(1'b0),
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) _TECHMAP_REPLACE_ (
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.D(D),
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.D(D),
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.Q(Q),
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.CLK(C),
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.CLK(C),
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.nRSTZ(R),
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.nSR(nRST),
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.nSETZ(S)
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.Q(Q)
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);
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);
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endmodule
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endmodule
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@ -1,16 +1,45 @@
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module GP_DFF(input D, CLK, nRSTZ, nSETZ, output reg Q);
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module GP_DFF(input D, CLK, output reg Q);
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parameter [0:0] INIT = 1'bx;
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parameter [0:0] INIT = 1'bx;
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initial Q = INIT;
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initial Q = INIT;
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always @(posedge CLK, negedge nRSTZ, negedge nSETZ) begin
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always @(posedge CLK) begin
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if (!nRSTZ)
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Q <= D;
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Q <= 1'b0;
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end
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else if (!nSETZ)
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endmodule
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module GP_DFFS(input D, CLK, nSET, output reg Q);
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parameter [0:0] INIT = 1'bx;
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initial Q = INIT;
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always @(posedge CLK, negedge nSET) begin
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if (!nSET)
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Q <= 1'b1;
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Q <= 1'b1;
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else
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else
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Q <= D;
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Q <= D;
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end
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end
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endmodule
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endmodule
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module GP_DFFR(input D, CLK, nRST, output reg Q);
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parameter [0:0] INIT = 1'bx;
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initial Q = INIT;
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always @(posedge CLK, negedge nRST) begin
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if (!nRST)
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Q <= 1'b0;
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else
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Q <= D;
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end
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endmodule
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module GP_DFFSR(input D, CLK, nSR, output reg Q);
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parameter [0:0] INIT = 1'bx;
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parameter [0:0] SRMODE = 1'bx;
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initial Q = INIT;
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always @(posedge CLK, negedge nSR) begin
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if (!nSR)
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Q <= SRMODE;
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else
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Q <= D;
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end
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endmodule
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module GP_2LUT(input IN0, IN1, output OUT);
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module GP_2LUT(input IN0, IN1, output OUT);
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parameter [3:0] INIT = 0;
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parameter [3:0] INIT = 0;
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assign OUT = INIT[{IN1, IN0}];
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assign OUT = INIT[{IN1, IN0}];
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@ -25,3 +54,11 @@ module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
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parameter [15:0] INIT = 0;
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parameter [15:0] INIT = 0;
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assign OUT = INIT[{IN3, IN2, IN1, IN0}];
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assign OUT = INIT[{IN3, IN2, IN1, IN0}];
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endmodule
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endmodule
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module GP4_VDD(output OUT);
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assign OUT = 1;
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endmodule
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module GP4_VSS(output OUT);
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assign OUT = 0;
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endmodule
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@ -1,5 +1,5 @@
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library(gp_dff) {
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library(gp_dff) {
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cell(GP_DFF_NOSR) {
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cell(GP_DFF) {
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area: 1;
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area: 1;
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ff("IQ", "IQN") { clocked_on: CLK;
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ff("IQ", "IQN") { clocked_on: CLK;
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next_state: D; }
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next_state: D; }
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@ -9,18 +9,28 @@ library(gp_dff) {
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pin(Q) { direction: output;
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pin(Q) { direction: output;
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function: "IQ"; }
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function: "IQ"; }
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}
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}
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cell(GP_DFF_SR) {
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cell(GP_DFFS) {
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area: 1;
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area: 1;
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ff("IQ", "IQN") { clocked_on: CLK;
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ff("IQ", "IQN") { clocked_on: CLK;
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next_state: D;
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next_state: D;
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preset: "nSETZ'";
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preset: "nSET'"; }
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clear: "nRSTZ'"; }
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pin(CLK) { direction: input;
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pin(CLK) { direction: input;
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clock: true; }
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clock: true; }
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pin(D) { direction: input; }
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pin(D) { direction: input; }
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pin(Q) { direction: output;
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pin(Q) { direction: output;
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function: "IQ"; }
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function: "IQ"; }
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pin(nRSTZ) { direction: input; }
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pin(nSET) { direction: input; }
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pin(nSETZ) { direction: input; }
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}
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cell(GP_DFFR) {
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area: 1;
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ff("IQ", "IQN") { clocked_on: CLK;
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next_state: D;
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clear: "nRST'"; }
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pin(CLK) { direction: input;
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clock: true; }
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pin(D) { direction: input; }
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pin(Q) { direction: output;
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function: "IQ"; }
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pin(nRST) { direction: input; }
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}
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}
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}
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}
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@ -97,6 +97,7 @@ struct SynthGreenPAK4Pass : public Pass {
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log(" clean\n");
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log(" clean\n");
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log("\n");
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log("\n");
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log(" map_cells:\n");
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log(" map_cells:\n");
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log(" dfflibmap -liberty +/greenpak4/gp_dff.lib\n");
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log(" techmap -map +/greenpak4/cells_map.v\n");
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log(" techmap -map +/greenpak4/cells_map.v\n");
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log(" dffinit -ff GP_DFF Q INIT\n");
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log(" dffinit -ff GP_DFF Q INIT\n");
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log(" clean\n");
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log(" clean\n");
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@ -205,6 +206,7 @@ struct SynthGreenPAK4Pass : public Pass {
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if (check_label(active, run_from, run_to, "map_cells"))
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if (check_label(active, run_from, run_to, "map_cells"))
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{
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{
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Pass::call(design, "dfflibmap -liberty +/greenpak4/gp_dff.lib");
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Pass::call(design, "techmap -map +/greenpak4/cells_map.v");
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Pass::call(design, "techmap -map +/greenpak4/cells_map.v");
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Pass::call(design, "dffinit -ff GP_DFF Q INIT");
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Pass::call(design, "dffinit -ff GP_DFF Q INIT");
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Pass::call(design, "clean");
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Pass::call(design, "clean");
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