mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-05 10:50:25 +00:00
Code Activity

Added GP_DFFS, GP_DFFR, and GP_DFFSR

Browse source
This commit is contained in:
Clifford Wolf 2016-03-23 08:46:10 +01:00
parent 456c10f16e
commit b4bf787f10
4 changed files with 76 additions and 21 deletions
Download patch file Download diff file Expand all files Collapse all files

47
techlibs/greenpak4/cells_sim.v
View file

@ -1,16 +1,45 @@
module GP_DFF(input D, CLK, nRSTZ, nSETZ, output reg Q);
module GP_DFF(input D, CLK, output reg Q);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(posedge CLK, negedge nRSTZ, negedge nSETZ) begin
if (!nRSTZ)
Q <= 1'b0;
else if (!nSETZ)
always @(posedge CLK) begin
Q <= D;
end
endmodule
module GP_DFFS(input D, CLK, nSET, output reg Q);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(posedge CLK, negedge nSET) begin
if (!nSET)
Q <= 1'b1;
else
Q <= D;
end
endmodule
module GP_DFFR(input D, CLK, nRST, output reg Q);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(posedge CLK, negedge nRST) begin
if (!nRST)
Q <= 1'b0;
else
Q <= D;
end
endmodule
module GP_DFFSR(input D, CLK, nSR, output reg Q);
parameter [0:0] INIT = 1'bx;
parameter [0:0] SRMODE = 1'bx;
initial Q = INIT;
always @(posedge CLK, negedge nSR) begin
if (!nSR)
Q <= SRMODE;
else
Q <= D;
end
endmodule
module GP_2LUT(input IN0, IN1, output OUT);
parameter [3:0] INIT = 0;
assign OUT = INIT[{IN1, IN0}];
@ -25,3 +54,11 @@ module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
parameter [15:0] INIT = 0;
assign OUT = INIT[{IN3, IN2, IN1, IN0}];
endmodule
module GP4_VDD(output OUT);
assign OUT = 1;
endmodule
module GP4_VSS(output OUT);
assign OUT = 0;
endmodule