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https://github.com/YosysHQ/yosys
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parent
c39ebe6ae0
commit
b4a4cb081d
2 changed files with 37 additions and 1 deletions
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@ -801,11 +801,31 @@ struct TechmapWorker
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}
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}
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// Handle outputs first, as these cannot be remapped.
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for (auto &conn : cell->connections())
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{
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Wire *twire = tpl->wire(conn.first);
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if (!twire->port_output)
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continue;
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for (int i = 0; i < GetSize(conn.second); i++) {
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RTLIL::SigBit bit = sigmap(conn.second[i]);
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RTLIL::SigBit tplbit(twire, i);
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cellbits_to_tplbits[bit] = tplbit;
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}
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}
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// Now handle inputs, remapping as necessary.
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for (auto &conn : cell->connections())
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{
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Wire *twire = tpl->wire(conn.first);
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if (twire->port_output)
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continue;
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for (int i = 0; i < GetSize(conn.second); i++)
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{
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RTLIL::SigBit bit = sigmap(conn.second[i]);
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RTLIL::SigBit tplbit(tpl->wire(conn.first), i);
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RTLIL::SigBit tplbit(twire, i);
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if (bit.wire == nullptr)
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{
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@ -820,6 +840,7 @@ struct TechmapWorker
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else
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cellbits_to_tplbits[bit] = tplbit;
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}
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}
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RTLIL::SigSig port_conn;
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for (auto &it : port_connmap) {
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