3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-12 22:20:55 +00:00

add few more tests

This commit is contained in:
Miodrag Milanovic 2024-03-01 10:49:48 +01:00
parent 93543bd874
commit b4a17cccc3
2 changed files with 53 additions and 0 deletions

View file

@ -0,0 +1,12 @@
read_verilog ../common/tribuf.v
hierarchy -top tristate
proc
tribuf
flatten
synth
equiv_opt -assert -map +/nanoxplore/cells_sim.v -map +/simcells.v synth_nanoxplore # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd tristate # Constrain all select calls below inside the top module
#Internal cell type used. Need support it.
select -assert-count 1 t:$_TBUF_
select -assert-none t:$_TBUF_ %% t:* %D