mirror of
https://github.com/YosysHQ/yosys
synced 2025-06-19 04:13:39 +00:00
Merge remote-tracking branch 'origin/master' into xaig_dff
This commit is contained in:
Eddie Hung
commit
b454735bea
27 changed files with 159 additions and 91 deletions
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@ -1120,8 +1120,8 @@ module RAM16X1D_1 (
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endmodule
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module RAM32X1D (
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
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(* abc9_arrival=1153 *)
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L857
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(* abc9_arrival=1188 *)
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output DPO, SPO,
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input D,
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(* clkbuf_sink *)
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@ -1143,8 +1143,8 @@ module RAM32X1D (
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endmodule
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module RAM32X1D_1 (
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
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(* abc9_arrival=1153 *)
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L857
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(* abc9_arrival=1188 *)
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output DPO, SPO,
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input D,
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(* clkbuf_sink *)
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@ -1166,7 +1166,7 @@ module RAM32X1D_1 (
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endmodule
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module RAM64X1D (
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
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(* abc9_arrival=1153 *)
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output DPO, SPO,
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input D,
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@ -1189,7 +1189,7 @@ module RAM64X1D (
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endmodule
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module RAM64X1D_1 (
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
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(* abc9_arrival=1153 *)
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output DPO, SPO,
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input D,
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@ -1212,8 +1212,9 @@ module RAM64X1D_1 (
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endmodule
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module RAM128X1D (
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
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(* abc9_arrival=1153 *)
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
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// plus 204ps to cross MUXF7
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(* abc9_arrival=1357 *)
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output DPO, SPO,
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input D,
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(* clkbuf_sink *)
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@ -1252,9 +1253,18 @@ endmodule
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// Multi port.
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module RAM32M (
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
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(* abc9_arrival=1153 *)
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output [1:0] DOA, DOB, DOC, DOD,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L857
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(* abc9_arrival=1188 *)
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output [1:0] DOA,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L925
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(* abc9_arrival=1187 *)
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output [1:0] DOB,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L993
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(* abc9_arrival=1180 *)
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output [1:0] DOC,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1061
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(* abc9_arrival=1190 *)
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output [1:0] DOD,
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input [4:0] ADDRA, ADDRB, ADDRC, ADDRD,
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input [1:0] DIA, DIB, DIC, DID,
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(* clkbuf_sink *)
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@ -1355,9 +1365,18 @@ module RAM32M16 (
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endmodule
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module RAM64M (
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
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(* abc9_arrival=1153 *)
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output DOA, DOB, DOC, DOD,
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output DOA,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
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(* abc9_arrival=1161 *)
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output DOB,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025
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(* abc9_arrival=1158 *)
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output DOC,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
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(* abc9_arrival=1163 *)
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output DOD,
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input [5:0] ADDRA, ADDRB, ADDRC, ADDRD,
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input DIA, DIB, DIC, DID,
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(* clkbuf_sink *)
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@ -1516,7 +1535,7 @@ module SRL16 (
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endmodule
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module SRL16E (
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
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(* abc9_arrival=1472 *)
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output Q,
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input A0, A1, A2, A3, CE,
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@ -1580,9 +1599,10 @@ module SRLC16E (
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endmodule
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module SRLC32E (
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
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(* abc9_arrival=1472 *)
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output Q,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904
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(* abc9_arrival=1114 *)
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output Q31,
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input [4:0] A,
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@ -2224,7 +2244,7 @@ module DSP48E1 (
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parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
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initial begin
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`ifdef __ICARUS__
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`ifndef YOSYS
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if (AUTORESET_PATDET != "NO_RESET") $fatal(1, "Unsupported AUTORESET_PATDET value");
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if (SEL_MASK != "MASK") $fatal(1, "Unsupported SEL_MASK value");
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if (SEL_PATTERN != "PATTERN") $fatal(1, "Unsupported SEL_PATTERN value");
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@ -2387,12 +2407,12 @@ module DSP48E1 (
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case (OPMODEr[1:0])
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2'b00: X = 48'b0;
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2'b01: begin X = $signed(Mrx);
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`ifdef __ICARUS__
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`ifndef YOSYS
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if (OPMODEr[3:2] != 2'b01) $fatal(1, "OPMODEr[3:2] must be 2'b01 when OPMODEr[1:0] is 2'b01");
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`endif
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end
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2'b10: begin X = P;
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`ifdef __ICARUS__
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`ifndef YOSYS
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if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[1:0] is 2'b10");
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`endif
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end
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@ -2404,7 +2424,7 @@ module DSP48E1 (
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case (OPMODEr[3:2])
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2'b00: Y = 48'b0;
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2'b01: begin Y = 48'b0; // FIXME: more accurate partial product modelling?
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`ifdef __ICARUS__
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`ifndef YOSYS
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if (OPMODEr[1:0] != 2'b01) $fatal(1, "OPMODEr[1:0] must be 2'b01 when OPMODEr[3:2] is 2'b01");
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`endif
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end
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@ -2418,13 +2438,13 @@ module DSP48E1 (
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3'b000: Z = 48'b0;
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3'b001: Z = PCIN;
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3'b010: begin Z = P;
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`ifdef __ICARUS__
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`ifndef YOSYS
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if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[6:4] i0s 3'b010");
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`endif
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end
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3'b011: Z = Cr;
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3'b100: begin Z = P;
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`ifdef __ICARUS__
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`ifndef YOSYS
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if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[6:4] is 3'b100");
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if (OPMODEr[3:0] != 4'b1000) $fatal(1, "OPMODEr[3:0] must be 4'b1000 when OPMODEr[6:4] i0s 3'b100");
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`endif
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@ -111,7 +111,7 @@ struct SynthXilinxPass : public ScriptPass
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log(" run 'abc9' with -dff option\n");
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log("\n");
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log(" -retime\n");
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log(" run 'abc' with -dff option\n");
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log(" run 'abc' with '-dff -D 1' options\n");
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log("\n");
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log(" -abc9\n");
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log(" use new ABC9 flow (EXPERIMENTAL)\n");
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@ -566,9 +566,9 @@ struct SynthXilinxPass : public ScriptPass
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}
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else {
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if (nowidelut)
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run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
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run("abc -luts 2:2,3,6:5" + string(retime ? " -dff -D 1" : ""));
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else
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run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
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run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff -D 1" : ""));
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}
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run("clean");
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