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Detect undriven and error/warn

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This commit is contained in:
Gus Smith 2026-02-20 11:00:59 -08:00
parent cdc728b6f0
commit b454582f54
4 changed files with 108 additions and 5 deletions
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7
tests/sim/undriven_replay.v Normal file
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module undriven_replay (
input wire in,
output wire out,
output wire undrv
);
assign out = in;
endmodule

15
tests/sim/undriven_replay.vcd Normal file
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$version Yosys $end
$scope module undriven_replay $end
$var wire 1 ! in $end
$var wire 1 " out $end
$var wire 1 # undrv $end
$upscope $end
$enddefinitions $end
#0
b0 !
b0 "
b1 #
#10
b1 !
b1 "
b0 #

10
tests/sim/undriven_replay.ys Normal file
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read_verilog undriven_replay.v
prep -top undriven_replay
logger -expect error "Found 1 undriven signal in the replay trace" 1
sim -r undriven_replay.vcd -scope undriven_replay -q
logger -expect warning "Input trace contains undriven signal" 1
sim -r undriven_replay.vcd -scope undriven_replay -q -undriven-warn
sim -r undriven_replay.vcd -scope undriven_replay -q -no-undriven-check