From b438afc2d8439122b0e736ef5e7d59e37e0e0c2e Mon Sep 17 00:00:00 2001
From: Robert O'Callahan <rocallahan@google.com>
Date: Thu, 5 Feb 2026 18:20:31 +0000
Subject: [PATCH] Add 'init' attributes to RTLIL fuzzing

---
 tests/tools/rtlil-fuzz-grammar.json | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/tests/tools/rtlil-fuzz-grammar.json b/tests/tools/rtlil-fuzz-grammar.json
index c27b160f4..96af9bde3 100644
--- a/tests/tools/rtlil-fuzz-grammar.json
+++ b/tests/tools/rtlil-fuzz-grammar.json
@@ -8,7 +8,7 @@
 			"end\n"
 		]
 	],
-	"<WIRE>": [ [ "  wire width ", "<WIDTH>", " ", "<WIRE_MODE>", " ", "<WIRE_ID>", "\n" ] ],
+	"<WIRE>": [ [ "<WIRE_ATTRIBUTES>", "  wire width ", "<WIDTH>", " ", "<WIRE_MODE>", " ", "<WIRE_ID>", "\n" ] ],
 	"<WIDTH>": [ [ "1" ], [ "2" ], [ "3" ], [ "4" ], [ "32" ], [ "128" ] ],
 	"<WIRE_MODE>": [ [ "input ", "<PORT_ID>" ], [ "output ", "<PORT_ID>" ], [ "inout ", "<PORT_ID>" ], [] ],
 	"<CELL>": [
@@ -71,6 +71,7 @@
 			"  end\n"
 		]
 	],
+	"<WIRE_ATTRIBUTE>": [ [ "  attribute \\init ", "<CONST>", "\n" ] ],
 	"<WIRE_ID>": [ [ "\\wire_a" ], [ "\\wire_b" ], [ "\\wire_c" ], [ "\\wire_d" ], [ "\\wire_e" ], [ "\\wire_f" ], [ "\\wire_g" ], [ "\\wire_h" ], [ "\\wire_i" ], [ "\\wire_j" ] ],
 	"<CELL_ID>": [ [ "\\cell_a" ], [ "\\cell_b" ], [ "\\cell_c" ], [ "\\cell_d" ], [ "\\cell_e" ], [ "\\cell_f" ], [ "\\cell_g" ], [ "\\cell_h" ], [ "\\cell_i" ], [ "\\cell_j" ] ],
 	"<BLACKBOX_CELL>": [ [ "\\bb1" ], [ "\\bb2" ] ],
@@ -97,6 +98,7 @@
 	"<CONNECT>": [ [ "  connect ", "<SIGSPEC>", " ", "<SIGSPEC>", "\n" ] ],
 
 	"<WIRES>": [ [ ], [ "<WIRE>", "<WIRES>" ] ],
+	"<WIRE_ATTRIBUTES>": [ [ ], [ "<WIRE_ATTRIBUTE>", "<WIRE_ATTRIBUTES>" ] ],
 	"<CELLS>": [ [ ], [ "<CELL>", "<CELLS>" ] ],
 	"<BITS>": [ [ ], [ "<BIT>", "<BITS>" ] ],
 	"<CONNECTS>": [ [ ], [ "<CONNECT>", "<CONNECTS>" ] ],