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Move Pass::call() out of abc9_ops into abc9
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3 changed files with 63 additions and 68 deletions
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@ -710,6 +710,10 @@ struct XAigerWriter
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RTLIL::Module *holes_module = module->design->module(stringf("%s$holes", module->name.c_str()));
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log_assert(holes_module);
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for (auto cell : holes_module->cells())
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if (!cell->type.in("$_NOT_", "$_AND_"))
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log_error("Whitebox contents cannot be represented as AIG. Please verify whiteboxes are synthesisable.\n");
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module->design->selection_stack.emplace_back(false);
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module->design->selection().select(holes_module);
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