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Add logic param and integer bad syntax tests

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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
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Kamil Rakoczy 2020-07-06 09:05:34 +02:00
parent 7e83a51fc9
commit b422f2e4d0
3 changed files with 21 additions and 0 deletions
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6
tests/various/integer_range_bad_syntax.ys Normal file
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@ -0,0 +1,6 @@
logger -expect error "syntax error, unexpected" 1
read_verilog -sv <<EOT
module test_integer_range();
parameter integer [31:0] a = 0;
endmodule
EOT