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Gowin. Disable unsupported BSRAM mode in GW5A

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All supported (and planned to be supported) GW5A series chips do not
support the 2: Read-before-Write write mode.

Here, we prohibit the generation of BSRAM with this mode.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
This commit is contained in:
YRabbit 2025-10-21 12:36:06 +10:00
parent 37875fdedf
commit b3f7f0d8dc
3 changed files with 71 additions and 1 deletions
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69
techlibs/gowin/brams_gw5a.txt Normal file
View file

@ -0,0 +1,69 @@
ram block $__GOWIN_SP_ {
abits 14;
widths 1 2 4 9 18 36 per_port;
cost 128;
init no_undef;
port srsw "A" {
clock posedge;
clken;
option "RESET_MODE" "SYNC" {
rdsrst zero ungated;
}
option "RESET_MODE" "ASYNC" {
rdarst zero;
}
rdinit zero;
portoption "WRITE_MODE" 0 {
rdwr no_change;
}
portoption "WRITE_MODE" 1 {
rdwr new;
}
}
}
ram block $__GOWIN_DP_ {
abits 14;
widths 1 2 4 9 18 per_port;
cost 128;
init no_undef;
port srsw "A" "B" {
clock posedge;
clken;
option "RESET_MODE" "SYNC" {
rdsrst zero ungated;
}
option "RESET_MODE" "ASYNC" {
rdarst zero;
}
rdinit zero;
portoption "WRITE_MODE" 0 {
rdwr no_change;
}
portoption "WRITE_MODE" 1 {
rdwr new;
}
}
}
ram block $__GOWIN_SDP_ {
abits 14;
widths 1 2 4 9 18 36 per_port;
cost 128;
init no_undef;
port sr "R" {
clock posedge;
clken;
option "RESET_MODE" "SYNC" {
rdsrst zero ungated;
}
option "RESET_MODE" "ASYNC" {
rdarst zero;
}
rdinit zero;
}
port sw "W" {
clock posedge;
clken;
}
}