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Add NX_CY

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Lofty 2024-03-01 11:10:52 +01:00 • committed by Miodrag Milanovic
parent b4e9bb0d85
commit b3f59c9820
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6
techlibs/nanoxplore/cells_sim.v
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@ -33,3 +33,9 @@ always @(posedge clock, posedge async_reset)
else O <= I;
endmodule
module NX_CY(input A1, A2, A3, A4, B1, B2, B3, B4, (* abc9_carry *) input CI, output S1, S2, S3, S4, (* abc9_carry *) output CO);
parameter add_carry = 0;
assign {CO, S4, S3, S2, S1} = {A4, A3, A2, A1} + {B4, B3, B2, B1} + CI;
endmodule