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Merge cd370bf6d1 into c2291c10a6

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Robert O'Callahan 2025-09-10 11:49:17 +02:00 • committed by GitHub
commit b3baba4522
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79 changed files with 1002 additions and 484 deletions
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4
techlibs/gatemate/gatemate_foldinv.cc
View file

@ -82,7 +82,7 @@ struct FoldInvWorker {
Const result(State::S0, GetSize(lut));
for (int i = 0; i < GetSize(lut); i++) {
int j = i ^ (1 << bit);
result.bits()[j] = lut[i];
result.set(j, lut[i]);
}
return result;
}
@ -91,7 +91,7 @@ struct FoldInvWorker {
{
Const result(State::S0, GetSize(lut));
for (int i = 0; i < GetSize(lut); i++)
result.bits()[i] = (lut[i] == State::S1) ? State::S0 : State::S1;
result.set(i, (lut[i] == State::S1) ? State::S0 : State::S1);
return result;
}

8
techlibs/greenpak4/greenpak4_dffinv.cc
View file

@ -36,9 +36,9 @@ void invert_gp_dff(Cell *cell, bool invert_input)
Const initval = cell->getParam(ID::INIT);
if (GetSize(initval) >= 1) {
if (initval[0] == State::S0)
initval.bits()[0] = State::S1;
initval.set(0, State::S1);
else if (initval[0] == State::S1)
initval.bits()[0] = State::S0;
initval.set(0, State::S0);
cell->setParam(ID::INIT, initval);
}
@ -47,9 +47,9 @@ void invert_gp_dff(Cell *cell, bool invert_input)
Const srmode = cell->getParam(ID(SRMODE));
if (GetSize(srmode) >= 1) {
if (srmode[0] == State::S0)
srmode.bits()[0] = State::S1;
srmode.set(0, State::S1);
else if (srmode[0] == State::S1)
srmode.bits()[0] = State::S0;
srmode.set(0, State::S0);
cell->setParam(ID(SRMODE), srmode);
}
}

2
techlibs/ice40/ice40_dsp.cc
View file

@ -82,7 +82,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
SigSpec CD = st.sigCD;
if (CD.empty())
CD = RTLIL::Const(0, 32);
CD = RTLIL::Const(0);
else
log_assert(GetSize(CD) == 32);

2
techlibs/microchip/microchip_dffopt.cc
View file

@ -93,7 +93,7 @@ bool merge_lut(LutData &result, const LutData &data, const LutData select, bool
int lut_idx = i >> idx_data & ((1 << GetSize(data.second)) - 1);
new_bit = data.first[lut_idx] == State::S1;
}
result.first.bits()[i] = new_bit ? State::S1 : State::S0;
result.first.set(i, new_bit ? State::S1 : State::S0);
}
return true;
}

4
techlibs/microchip/microchip_dsp.cc
View file

@ -128,7 +128,7 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
continue;
for (int i = c.offset; i < c.offset + c.width; i++) {
log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx);
it->second.bits()[i] = State::Sx;
it->second.set(i, State::Sx);
}
}
};
@ -244,7 +244,7 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm)
continue;
for (int i = c.offset; i < c.offset + c.width; i++) {
log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx);
it->second.bits()[i] = State::Sx;
it->second.set(i, State::Sx);
}
}
};

2
techlibs/quicklogic/ql_bram_merge.cc
View file

@ -45,7 +45,7 @@ struct QlBramMergeWorker {
{
if(cell->type != split_cell_type) continue;
if(!cell->hasParam(ID(OPTION_SPLIT))) continue;
if(cell->getParam(ID(OPTION_SPLIT)) != RTLIL::Const(1, 32)) continue;
if(cell->getParam(ID(OPTION_SPLIT)) != RTLIL::Const(1)) continue;
mergeable_groups[get_key(cell)].insert(cell);
}
}

6
techlibs/quicklogic/ql_dsp_simd.cc
View file

@ -200,10 +200,8 @@ struct QlDspSimdPass : public Pass {
auto val_a = dsp_a->getParam(it);
auto val_b = dsp_b->getParam(it);
mode_bits.bits().insert(mode_bits.bits().end(),
val_a.begin(), val_a.end());
mode_bits.bits().insert(mode_bits.bits().end(),
val_b.begin(), val_b.end());
mode_bits.append(val_a);
mode_bits.append(val_b);
}
// Enable the fractured mode by connecting the control

6
techlibs/xilinx/xilinx_dffopt.cc
View file

@ -92,7 +92,7 @@ bool merge_lut(LutData &result, const LutData &data, const LutData select, bool
int lut_idx = i >> idx_data & ((1 << GetSize(data.second)) - 1);
new_bit = data.first[lut_idx] == State::S1;
}
result.first.bits()[i] = new_bit ? State::S1 : State::S0;
result.first.set(i, new_bit ? State::S1 : State::S0);
}
return true;
}
@ -211,8 +211,8 @@ lut_sigin_done:
Cell *cell_d = it_D->second.second;
if (cell->hasParam(ID(IS_D_INVERTED)) && cell->getParam(ID(IS_D_INVERTED)).as_bool()) {
// Flip all bits in the LUT.
for (int i = 0; i < GetSize(lut_d.first); i++)
lut_d.first.bits()[i] = (lut_d.first[i] == State::S1) ? State::S0 : State::S1;
for (auto bit : lut_d.first)
bit = (bit == State::S1) ? State::S0 : State::S1;
}
LutData lut_d_post_ce;

8
techlibs/xilinx/xilinx_dsp.cc
View file

@ -343,7 +343,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
// Since B is an exact power of 2, subtract 1
// by inverting all bits up until hitting
// that one hi bit
for (auto &b : B.bits())
for (auto b : B)
if (b == State::S0) b = State::S1;
else if (b == State::S1) {
b = State::S0;
@ -392,7 +392,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
continue;
for (int i = c.offset; i < c.offset+c.width; i++) {
log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx);
it->second.bits()[i] = State::Sx;
it->second.set(i, State::Sx);
}
}
};
@ -579,7 +579,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
continue;
for (int i = c.offset; i < c.offset+c.width; i++) {
log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx);
it->second.bits()[i] = State::Sx;
it->second.set(i, State::Sx);
}
}
};
@ -702,7 +702,7 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
continue;
for (int i = c.offset; i < c.offset+c.width; i++) {
log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx);
it->second.bits()[i] = State::Sx;
it->second.set(i, State::Sx);
}
}
};

10
techlibs/xilinx/xilinx_srl.cc
View file

@ -40,9 +40,8 @@ void run_fixed(xilinx_srl_pm &pm)
log_assert(Q.wire);
auto it = Q.wire->attributes.find(ID::init);
if (it != Q.wire->attributes.end()) {
auto &i = it->second.bits()[Q.offset];
initval.append(i);
i = State::Sx;
initval.append(it->second[Q.offset]);
it->second.set(Q.offset, State::Sx);
}
else
initval.append(State::Sx);
@ -121,9 +120,8 @@ void run_variable(xilinx_srl_pm &pm)
log_assert(Q.wire);
auto it = Q.wire->attributes.find(ID::init);
if (it != Q.wire->attributes.end()) {
auto &i = it->second.bits()[Q.offset];
initval.append(i);
i = State::Sx;
initval.append(it->second[Q.offset]);
it->second.set(Q.offset, State::Sx);
}
else
initval.append(State::Sx);