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Merge cd370bf6d1 into c2291c10a6

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Robert O'Callahan 2025-09-10 11:49:17 +02:00 • committed by GitHub
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79 changed files with 1002 additions and 484 deletions
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6
passes/cmds/bugpoint.cc
View file

@ -405,7 +405,11 @@ struct BugpointPass : public Pass {
for (auto it2 = sy->mem_write_actions.begin(); it2 != sy->mem_write_actions.end(); ++it2) {
auto &mask = it2->priority_mask;
if (GetSize(mask) > i) {
mask.bits().erase(mask.bits().begin() + i);
RTLIL::Const::Builder new_mask_builder(GetSize(mask) - 1);
for (int k = 0; k < GetSize(mask); k++)
if (k != i)
new_mask_builder.push_back(mask[k]);
mask = new_mask_builder.build();
}
}
return design_copy;

6
passes/cmds/clean_zerowidth.cc
View file

@ -158,11 +158,11 @@ struct CleanZeroWidthPass : public Pass {
continue;
if (GetSize(memwr.address) == 0)
memwr.address = State::S0;
Const priority_mask;
RTLIL::Const::Builder new_mask_bits(swizzle.size());
for (auto x : swizzle) {
priority_mask.bits().push_back(memwr.priority_mask[x]);
new_mask_bits.push_back(memwr.priority_mask[x]);
}
memwr.priority_mask = priority_mask;
memwr.priority_mask = new_mask_bits.build();
swizzle.push_back(i);
new_memwr_actions.push_back(memwr);
}

6
passes/cmds/dft_tag.cc
View file

@ -884,8 +884,10 @@ struct DftTagWorker {
{
if (sig_a.is_fully_const()) {
auto const_val = sig_a.as_const();
for (State& bit : const_val.bits())
bit = bit == State::S0 ? State::S1 : bit == State::S1 ? State::S0 : bit;
for (auto bit : const_val) {
State b = bit;
bit = b == State::S0 ? State::S1 : b == State::S1 ? State::S0 : b;
}
return const_val;
}
return module->Not(name, sig_a);

8
passes/cmds/setundef.cc
View file

@ -243,7 +243,7 @@ struct SetundefPass : public Pass {
{
for (auto *cell : module->selected_cells()) {
for (auto &parameter : cell->parameters) {
for (auto &bit : parameter.second.bits()) {
for (auto bit : parameter.second) {
if (bit > RTLIL::State::S1)
bit = worker.next_bit();
}
@ -390,12 +390,12 @@ struct SetundefPass : public Pass {
for (auto wire : initwires)
{
Const &initval = wire->attributes[ID::init];
initval.bits().resize(GetSize(wire), State::Sx);
initval.resize(GetSize(wire), State::Sx);
for (int i = 0; i < GetSize(wire); i++) {
SigBit bit = sigmap(SigBit(wire, i));
if (initval[i] == State::Sx && ffbits.count(bit)) {
initval.bits()[i] = worker.next_bit();
initval.set(i, worker.next_bit());
ffbits.erase(bit);
}
}
@ -421,7 +421,7 @@ struct SetundefPass : public Pass {
continue;
Const &initval = wire->attributes[ID::init];
initval.bits().resize(GetSize(wire), State::Sx);
initval.resize(GetSize(wire), State::Sx);
if (initval.is_fully_undef()) {
wire->attributes.erase(ID::init);

7
passes/cmds/splitnets.cc
View file

@ -75,10 +75,11 @@ struct SplitnetsWorker
it = wire->attributes.find(ID::init);
if (it != wire->attributes.end()) {
Const old_init = it->second, new_init;
Const old_init = it->second;
RTLIL::Const::Builder new_init_bits_builder(width);
for (int i = offset; i < offset+width; i++)
new_init.bits().push_back(i < GetSize(old_init) ? old_init.at(i) : State::Sx);
new_wire->attributes.emplace(ID::init, new_init);
new_init_bits_builder.push_back(i < GetSize(old_init) ? old_init.at(i) : State::Sx);
new_wire->attributes.emplace(ID::init, new_init_bits_builder.build());
}
std::vector<RTLIL::SigBit> sigvec = RTLIL::SigSpec(new_wire).to_sigbit_vector();

12
passes/cmds/xprop.cc
View file

@ -828,9 +828,9 @@ struct XpropWorker
auto init_q_is_1 = init_q;
auto init_q_is_x = init_q;
for (auto &bit : init_q_is_1.bits())
for (auto bit : init_q_is_1)
bit = bit == State::S1 ? State::S1 : State::S0;
for (auto &bit : init_q_is_x.bits())
for (auto bit : init_q_is_x)
bit = bit == State::Sx ? State::S1 : State::S0;
initvals.remove_init(sig_q);
@ -865,14 +865,14 @@ struct XpropWorker
auto init_q_is_x = init_q;
if (ff.is_anyinit) {
for (auto &bit : init_q_is_1.bits())
for (auto bit : init_q_is_1)
bit = State::Sx;
for (auto &bit : init_q_is_x.bits())
for (auto bit : init_q_is_x)
bit = State::S0;
} else {
for (auto &bit : init_q_is_1.bits())
for (auto bit : init_q_is_1)
bit = bit == State::S1 ? State::S1 : State::S0;
for (auto &bit : init_q_is_x.bits())
for (auto bit : init_q_is_x)
bit = bit == State::Sx ? State::S1 : State::S0;
}

2
passes/fsm/fsm_extract.cc
View file

@ -171,7 +171,7 @@ undef_bit_in_next_state:
if (tr.ctrl_in.at(it.second) == State::S1 && exclusive_ctrls.count(it.first) != 0)
for (auto &dc_bit : exclusive_ctrls.at(it.first))
if (ctrl_in_bit_indices.count(dc_bit))
tr.ctrl_in.bits().at(ctrl_in_bit_indices.at(dc_bit)) = RTLIL::State::Sa;
tr.ctrl_in.set(ctrl_in_bit_indices.at(dc_bit), RTLIL::State::Sa);
RTLIL::Const log_state_in = RTLIL::Const(RTLIL::State::Sx, fsm_data.state_bits);
if (state_in >= 0)

2
passes/fsm/fsm_map.cc
View file

@ -176,7 +176,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
state_dff->type = ID($adff);
state_dff->parameters[ID::ARST_POLARITY] = fsm_cell->parameters[ID::ARST_POLARITY];
state_dff->parameters[ID::ARST_VALUE] = fsm_data.state_table[fsm_data.reset_state];
for (auto &bit : state_dff->parameters[ID::ARST_VALUE].bits())
for (auto bit : state_dff->parameters[ID::ARST_VALUE])
if (bit != RTLIL::State::S1)
bit = RTLIL::State::S0;
state_dff->setPort(ID::ARST, fsm_cell->getPort(ID::ARST));

21
passes/fsm/fsm_opt.cc
View file

@ -169,13 +169,16 @@ struct FsmOpt
for (auto tr : fsm_data.transition_table)
{
RTLIL::State &si = tr.ctrl_in.bits()[i];
RTLIL::State &sj = tr.ctrl_in.bits()[j];
RTLIL::State si = tr.ctrl_in[i];
RTLIL::State sj = tr.ctrl_in[j];
if (si > RTLIL::State::S1)
if (si > RTLIL::State::S1) {
si = sj;
else if (sj > RTLIL::State::S1)
tr.ctrl_in.set(i, si);
} else if (sj > RTLIL::State::S1) {
sj = si;
tr.ctrl_in.set(j, sj);
}
if (si == sj) {
RTLIL::SigSpec tmp(tr.ctrl_in);
@ -207,8 +210,8 @@ struct FsmOpt
for (auto tr : fsm_data.transition_table)
{
RTLIL::State &si = tr.ctrl_in.bits()[i];
RTLIL::State &sj = tr.ctrl_out.bits()[j];
RTLIL::State si = tr.ctrl_in[i];
RTLIL::State sj = tr.ctrl_out[j];
if (si > RTLIL::State::S1 || si == sj) {
RTLIL::SigSpec tmp(tr.ctrl_in);
@ -240,14 +243,14 @@ struct FsmOpt
RTLIL::Const other_pattern = pattern;
if (pattern[bit] == RTLIL::State::S1)
other_pattern.bits()[bit] = RTLIL::State::S0;
other_pattern.set(bit, RTLIL::State::S0);
else
other_pattern.bits()[bit] = RTLIL::State::S1;
other_pattern.set(bit, RTLIL::State::S1);
if (set.count(other_pattern) > 0) {
log(" Merging pattern %s and %s from group (%d %d %s).\n", log_signal(pattern), log_signal(other_pattern),
tr.state_in, tr.state_out, log_signal(tr.ctrl_out));
other_pattern.bits()[bit] = RTLIL::State::Sa;
other_pattern.set(bit, RTLIL::State::Sa);
new_set.insert(other_pattern);
did_something = true;
continue;

2
passes/fsm/fsm_recode.cc
View file

@ -106,7 +106,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs
if (encoding == "one-hot") {
new_code = RTLIL::Const(RTLIL::State::Sa, fsm_data.state_bits);
new_code.bits()[state_idx] = RTLIL::State::S1;
new_code.set(state_idx, RTLIL::State::S1);
} else
if (encoding == "binary") {
new_code = RTLIL::Const(state_idx, fsm_data.state_bits);

49
passes/fsm/fsmdata.h
View file

@ -45,35 +45,27 @@ struct FsmData
cell->parameters[ID::STATE_NUM] = RTLIL::Const(state_table.size());
cell->parameters[ID::STATE_NUM_LOG2] = RTLIL::Const(state_num_log2);
cell->parameters[ID::STATE_RST] = RTLIL::Const(reset_state);
cell->parameters[ID::STATE_TABLE] = RTLIL::Const();
for (int i = 0; i < int(state_table.size()); i++) {
std::vector<RTLIL::State> &bits_table = cell->parameters[ID::STATE_TABLE].bits();
std::vector<RTLIL::State> &bits_state = state_table[i].bits();
bits_table.insert(bits_table.end(), bits_state.begin(), bits_state.end());
}
RTLIL::Const cell_state_table;
for (const RTLIL::Const &c : state_table)
cell_state_table.append(c);
cell->parameters[ID::STATE_TABLE] = std::move(cell_state_table);
cell->parameters[ID::TRANS_NUM] = RTLIL::Const(transition_table.size());
cell->parameters[ID::TRANS_TABLE] = RTLIL::Const();
RTLIL::Const cell_trans_table;
for (int i = 0; i < int(transition_table.size()); i++)
{
std::vector<RTLIL::State> &bits_table = cell->parameters[ID::TRANS_TABLE].bits();
transition_t &tr = transition_table[i];
RTLIL::Const const_state_in = RTLIL::Const(tr.state_in, state_num_log2);
RTLIL::Const const_state_out = RTLIL::Const(tr.state_out, state_num_log2);
std::vector<RTLIL::State> &bits_state_in = const_state_in.bits();
std::vector<RTLIL::State> &bits_state_out = const_state_out.bits();
std::vector<RTLIL::State> &bits_ctrl_in = tr.ctrl_in.bits();
std::vector<RTLIL::State> &bits_ctrl_out = tr.ctrl_out.bits();
// append lsb first
bits_table.insert(bits_table.end(), bits_ctrl_out.begin(), bits_ctrl_out.end());
bits_table.insert(bits_table.end(), bits_state_out.begin(), bits_state_out.end());
bits_table.insert(bits_table.end(), bits_ctrl_in.begin(), bits_ctrl_in.end());
bits_table.insert(bits_table.end(), bits_state_in.begin(), bits_state_in.end());
cell_trans_table.append(tr.ctrl_out);
cell_trans_table.append(const_state_out);
cell_trans_table.append(tr.ctrl_in);
cell_trans_table.append(const_state_in);
}
cell->parameters[ID::TRANS_TABLE] = std::move(cell_trans_table);
}
void copy_from_cell(RTLIL::Cell *cell)
@ -95,25 +87,18 @@ struct FsmData
const RTLIL::Const &trans_table = cell->parameters[ID::TRANS_TABLE];
for (int i = 0; i < state_num; i++) {
RTLIL::Const state_code;
int off_begin = i*state_bits, off_end = off_begin + state_bits;
state_code.bits().insert(state_code.bits().begin(), state_table.begin()+off_begin, state_table.begin()+off_end);
int off_begin = i*state_bits;
RTLIL::Const state_code = state_table.extract(off_begin, state_bits);
this->state_table.push_back(state_code);
}
for (int i = 0; i < trans_num; i++)
{
auto off_ctrl_out = trans_table.begin() + i*(num_inputs+num_outputs+2*state_num_log2);
auto off_state_out = off_ctrl_out + num_outputs;
auto off_ctrl_in = off_state_out + state_num_log2;
auto off_state_in = off_ctrl_in + num_inputs;
auto off_end = off_state_in + state_num_log2;
RTLIL::Const state_in, state_out, ctrl_in, ctrl_out;
ctrl_out.bits().insert(ctrl_out.bits().begin(), off_ctrl_out, off_state_out);
state_out.bits().insert(state_out.bits().begin(), off_state_out, off_ctrl_in);
ctrl_in.bits().insert(ctrl_in.bits().begin(), off_ctrl_in, off_state_in);
state_in.bits().insert(state_in.bits().begin(), off_state_in, off_end);
int base_offset = i*(num_inputs+num_outputs+2*state_num_log2);
RTLIL::Const ctrl_out = trans_table.extract(base_offset, num_outputs);
RTLIL::Const state_out = trans_table.extract(base_offset + num_outputs, state_num_log2);
RTLIL::Const ctrl_in = trans_table.extract(base_offset + num_outputs + state_num_log2, num_inputs);
RTLIL::Const state_in = trans_table.extract(base_offset + num_outputs + state_num_log2 + num_inputs, state_num_log2);
transition_t tr;
tr.state_in = state_in.as_int();

6
passes/hierarchy/submod.cc
View file

@ -79,7 +79,7 @@ struct SubmodWorker
flag_wire(c.wire, create, set_int_used, set_ext_driven, set_ext_used);
if (set_int_driven)
for (int i = c.offset; i < c.offset+c.width; i++) {
wire_flags.at(c.wire).is_int_driven.bits()[i] = State::S1;
wire_flags.at(c.wire).is_int_driven.set(i, State::S1);
flag_found_something = true;
}
}
@ -185,8 +185,8 @@ struct SubmodWorker
auto it = sig[i].wire->attributes.find(ID::init);
if (it != sig[i].wire->attributes.end()) {
auto jt = new_wire->attributes.insert(std::make_pair(ID::init, Const(State::Sx, GetSize(sig)))).first;
jt->second.bits()[i] = it->second[sig[i].offset];
it->second.bits()[sig[i].offset] = State::Sx;
jt->second.set(i, it->second[sig[i].offset]);
it->second.set(sig[i].offset, State::Sx);
}
}
}

10
passes/memory/memory_bram.cc
View file

@ -848,9 +848,9 @@ grow_read_ports:;
for (int i = 0; i < mem.width; i++)
if (shuffle_map[i] != -1) {
module->connect(port.data[shuffle_map[i]], new_data[i]);
new_init_value.bits()[i] = port.init_value[shuffle_map[i]];
new_arst_value.bits()[i] = port.arst_value[shuffle_map[i]];
new_srst_value.bits()[i] = port.srst_value[shuffle_map[i]];
new_init_value.set(i, port.init_value[shuffle_map[i]]);
new_arst_value.set(i, port.arst_value[shuffle_map[i]]);
new_srst_value.set(i, port.srst_value[shuffle_map[i]]);
}
port.data = new_data;
port.init_value = new_init_value;
@ -887,9 +887,9 @@ grow_read_ports:;
for (int i = 0; i < init_size; i++)
for (int j = 0; j < bram.dbits; j++)
if (init_offset+i < GetSize(initdata) && init_offset+i >= 0)
initparam.bits()[i*bram.dbits+j] = initdata[init_offset+i][init_shift+j];
initparam.set(i*bram.dbits+j, initdata[init_offset+i][init_shift+j]);
else
initparam.bits()[i*bram.dbits+j] = State::Sx;
initparam.set(i*bram.dbits+j, State::Sx);
c->setParam(ID::INIT, initparam);
}

7
passes/memory/memory_share.cc
View file

@ -60,16 +60,17 @@ struct MemoryShareWorker
bool merge_rst_value(Mem &mem, Const &res, int wide_log2, const Const &src1, int sub1, const Const &src2, int sub2) {
res = Const(State::Sx, mem.width << wide_log2);
for (int i = 0; i < GetSize(src1); i++)
res.bits()[i + sub1 * mem.width] = src1[i];
res.set(i + sub1 * mem.width, src1[i]);
for (int i = 0; i < GetSize(src2); i++) {
if (src2[i] == State::Sx)
continue;
auto &dst = res.bits()[i + sub2 * mem.width];
int idx = i + sub2 * mem.width;
RTLIL::State dst = res[idx];
if (dst == src2[i])
continue;
if (dst != State::Sx)
return false;
dst = src2[i];
res.set(idx, src2[i]);
}
return true;
}

6
passes/opt/opt_clean.cc
View file

@ -406,7 +406,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
for (int i = 0; i < wire->width; i++) {
auto it = init_bits.find(RTLIL::SigBit(wire, i));
if (it != init_bits.end()) {
val.bits()[i] = it->second;
val.set(i, it->second);
found = true;
}
}
@ -425,7 +425,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
if (wire->attributes.count(ID::init))
initval = wire->attributes.at(ID::init);
if (GetSize(initval) != GetSize(wire))
initval.bits().resize(GetSize(wire), State::Sx);
initval.resize(GetSize(wire), State::Sx);
if (initval.is_fully_undef())
wire->attributes.erase(ID::init);
@ -457,7 +457,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
if (s1[i] != s2[i]) {
if (s2[i] == State::Sx && (initval[i] == State::S0 || initval[i] == State::S1)) {
s2[i] = initval[i];
initval.bits()[i] = State::Sx;
initval.set(i, State::Sx);
}
new_conn.first.append(s1[i]);
new_conn.second.append(s2[i]);

22
passes/opt/opt_dff.cc
View file

@ -405,27 +405,29 @@ struct OptDffWorker
} else if (ff.pol_clr == ff.pol_set) {
// Try a more complex conversion to plain async reset.
State val_neutral = ff.pol_set ? State::S0 : State::S1;
Const val_arst;
SigBit sig_arst;
if (ff.sig_clr[0] == val_neutral)
sig_arst = ff.sig_set[0];
else
sig_arst = ff.sig_clr[0];
bool failed = false;
Const::Builder val_arst_builder(ff.width);
for (int i = 0; i < ff.width; i++) {
if (ff.sig_clr[i] == sig_arst && ff.sig_set[i] == val_neutral)
val_arst.bits().push_back(State::S0);
val_arst_builder.push_back(State::S0);
else if (ff.sig_set[i] == sig_arst && ff.sig_clr[i] == val_neutral)
val_arst.bits().push_back(State::S1);
else
val_arst_builder.push_back(State::S1);
else {
failed = true;
break;
}
}
if (!failed) {
log("Converting CLR/SET to ARST on %s (%s) from module %s.\n",
log_id(cell), log_id(cell->type), log_id(module));
ff.has_sr = false;
ff.has_arst = true;
ff.val_arst = val_arst;
ff.val_arst = val_arst_builder.build();
ff.sig_arst = sig_arst;
ff.pol_arst = ff.pol_clr;
changed = true;
@ -637,7 +639,7 @@ struct OptDffWorker
// Try to merge sync resets.
std::map<ctrls_t, std::vector<int>> groups;
std::vector<int> remaining_indices;
Const val_srst;
Const::Builder val_srst_builder(ff.width);
for (int i = 0 ; i < ff.width; i++) {
ctrls_t resets;
@ -679,16 +681,18 @@ struct OptDffWorker
groups[resets].push_back(i);
} else
remaining_indices.push_back(i);
val_srst.bits().push_back(reset_val);
val_srst_builder.push_back(reset_val);
}
Const val_srst = val_srst_builder.build();
for (auto &it : groups) {
FfData new_ff = ff.slice(it.second);
new_ff.val_srst = Const();
Const::Builder new_val_srst_builder(new_ff.width);
for (int i = 0; i < new_ff.width; i++) {
int j = it.second[i];
new_ff.val_srst.bits().push_back(val_srst[j]);
new_val_srst_builder.push_back(val_srst[j]);
}
new_ff.val_srst = new_val_srst_builder.build();
ctrl_t srst = combine_resets(it.first, ff.is_fine);
new_ff.has_srst = true;

4
passes/opt/opt_expr.cc
View file

@ -83,7 +83,7 @@ void replace_undriven(RTLIL::Module *module, const CellTypes &ct)
auto cursor = initbits.find(bit);
if (cursor != initbits.end()) {
revisit_initwires.insert(cursor->second.first);
val.bits()[i] = cursor->second.second;
val.set(i, cursor->second.second);
}
}
@ -101,7 +101,7 @@ void replace_undriven(RTLIL::Module *module, const CellTypes &ct)
Const initval = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(initval) && i < GetSize(wire); i++) {
if (SigBit(initval[i]) == sig[i])
initval.bits()[i] = State::Sx;
initval.set(i, State::Sx);
}
if (initval.is_fully_undef()) {
log_debug("Removing init attribute from %s/%s.\n", log_id(module), log_id(wire));

15
passes/opt/opt_ffinv.cc
View file

@ -96,10 +96,10 @@ struct OptFfInvWorker
}
}
Const mask = lut->getParam(ID::LUT);
Const new_mask;
for (int j = 0; j < (1 << GetSize(sig_a)); j++) {
new_mask.bits().push_back(mask[j ^ flip_mask]);
}
Const::Builder new_mask_builder(1 << GetSize(sig_a));
for (int j = 0; j < (1 << GetSize(sig_a)); j++)
new_mask_builder.push_back(mask[j ^ flip_mask]);
Const new_mask = new_mask_builder.build();
if (GetSize(sig_a) == 1 && new_mask.as_int() == 2) {
module->connect(lut->getPort(ID::Y), ff.sig_q);
module->remove(lut);
@ -178,13 +178,14 @@ struct OptFfInvWorker
if (d_lut->type == ID($lut)) {
Const mask = d_lut->getParam(ID::LUT);
Const new_mask;
Const::Builder new_mask_builder(GetSize(mask));
for (int i = 0; i < GetSize(mask); i++) {
if (mask[i] == State::S0)
new_mask.bits().push_back(State::S1);
new_mask_builder.push_back(State::S1);
else
new_mask.bits().push_back(State::S0);
new_mask_builder.push_back(State::S0);
}
Const new_mask = new_mask_builder.build();
d_lut->setParam(ID::LUT, new_mask);
if (d_lut->getParam(ID::WIDTH) == 1 && new_mask.as_int() == 2) {
module->connect(ff.sig_d, d_lut->getPort(ID::A));

2
passes/opt/opt_lut.cc
View file

@ -493,7 +493,7 @@ struct OptLutWorker
eval_inputs[lutM_new_inputs[i]] = (eval >> i) & 1;
}
eval_inputs[lutA_output] = evaluate_lut(lutA, eval_inputs);
lutM_new_table.bits()[eval] = (RTLIL::State) evaluate_lut(lutB, eval_inputs);
lutM_new_table.set(eval, (RTLIL::State) evaluate_lut(lutB, eval_inputs));
}
log_debug(" Cell A truth table: %s.\n", lutA->getParam(ID::LUT).as_string().c_str());

2
passes/opt/opt_lut_ins.cc
View file

@ -213,7 +213,7 @@ struct OptLutInsPass : public Pass {
}
lidx |= val << j;
}
new_lut.bits()[i] = lut[lidx];
new_lut.set(i, lut[lidx]);
}
// For lattice, and gowin do not replace with a const driver — the nextpnr
// packer requires a complete set of LUTs for wide LUT muxes.

30
passes/opt/opt_mem.cc
View file

@ -175,36 +175,36 @@ struct OptMemPass : public Pass {
}
for (auto &port: mem.rd_ports) {
SigSpec new_data;
Const new_init;
Const new_arst;
Const new_srst;
Const::Builder new_init_bits;
Const::Builder new_arst_bits;
Const::Builder new_srst_bits;
for (int sub = 0; sub < (1 << port.wide_log2); sub++) {
for (auto i: swizzle) {
int bidx = sub * mem.width + i;
new_data.append(port.data[bidx]);
new_init.bits().push_back(port.init_value[bidx]);
new_arst.bits().push_back(port.arst_value[bidx]);
new_srst.bits().push_back(port.srst_value[bidx]);
new_init_bits.push_back(port.init_value[bidx]);
new_arst_bits.push_back(port.arst_value[bidx]);
new_srst_bits.push_back(port.srst_value[bidx]);
}
}
port.data = new_data;
port.init_value = new_init;
port.arst_value = new_arst;
port.srst_value = new_srst;
port.init_value = new_init_bits.build();
port.arst_value = new_arst_bits.build();
port.srst_value = new_srst_bits.build();
}
for (auto &init: mem.inits) {
Const new_data;
Const new_en;
Const::Builder new_data_bits;
for (int s = 0; s < GetSize(init.data); s += mem.width) {
for (auto i: swizzle) {
new_data.bits().push_back(init.data[s + i]);
new_data_bits.push_back(init.data[s + i]);
}
}
init.data = new_data_bits.build();
Const::Builder new_en_bits;
for (auto i: swizzle) {
new_en.bits().push_back(init.en[i]);
new_en_bits.push_back(init.en[i]);
}
init.data = new_data;
init.en = new_en;
init.en = new_en_bits.build();
}
mem.width = GetSize(swizzle);
changed = true;

16
passes/opt/pmux2shiftx.cc
View file

@ -321,11 +321,12 @@ struct Pmux2ShiftxPass : public Pass {
bits.sort();
pair<SigSpec, Const> entry;
RTLIL::Const::Builder entry_bits_builder(GetSize(bits));
for (auto it : bits) {
entry.first.append(it.first);
entry.second.bits().push_back(it.second);
entry_bits_builder.push_back(it.second);
}
entry.second = entry_bits_builder.build();
eqdb[sigmap(cell->getPort(ID::Y)[0])] = entry;
goto next_cell;
@ -342,11 +343,12 @@ struct Pmux2ShiftxPass : public Pass {
bits.sort();
pair<SigSpec, Const> entry;
RTLIL::Const::Builder entry_bits_builder(GetSize(bits));
for (auto it : bits) {
entry.first.append(it.first);
entry.second.bits().push_back(it.second);
entry_bits_builder.push_back(it.second);
}
entry.second = entry_bits_builder.build();
eqdb[sigmap(cell->getPort(ID::Y)[0])] = entry;
goto next_cell;
@ -591,7 +593,7 @@ struct Pmux2ShiftxPass : public Pass {
used_src_columns[best_src_col] = true;
perm_new_from_old[dst_col] = best_src_col;
perm_xormask.bits()[dst_col] = best_inv ? State::S1 : State::S0;
perm_xormask.set(dst_col, best_inv ? State::S1 : State::S0);
}
}
@ -614,7 +616,7 @@ struct Pmux2ShiftxPass : public Pass {
Const new_c(State::S0, GetSize(old_c));
for (int i = 0; i < GetSize(old_c); i++)
new_c.bits()[i] = old_c[perm_new_from_old[i]];
new_c.set(i, old_c[perm_new_from_old[i]]);
Const new_c_before_xor = new_c;
new_c = const_xor(new_c, perm_xormask, false, false, GetSize(new_c));
@ -687,7 +689,7 @@ struct Pmux2ShiftxPass : public Pass {
if (!full_case) {
Const enable_mask(State::S0, max_choice+1);
for (auto &it : perm_choices)
enable_mask.bits()[it.first.as_int()] = State::S1;
enable_mask.set(it.first.as_int(), State::S1);
en = module->addWire(NEW_ID);
module->addShift(NEW_ID, enable_mask, cmp, en, false, src);
}

26
passes/opt/share.cc
View file

@ -790,12 +790,13 @@ struct ShareWorker
}
p.first = RTLIL::SigSpec();
p.second.bits().clear();
RTLIL::Const::Builder new_bits(p_bits.size());
for (auto &it : p_bits) {
p.first.append(it.first);
p.second.bits().push_back(it.second);
new_bits.push_back(it.second);
}
p.second = new_bits.build();
return true;
}
@ -818,9 +819,9 @@ struct ShareWorker
auto otherval = val;
if (otherval[i] == State::S0)
otherval.bits()[i] = State::S1;
otherval.set(i, State::S1);
else if (otherval[i] == State::S1)
otherval.bits()[i] = State::S0;
otherval.set(i, State::S0);
else
continue;
@ -829,8 +830,11 @@ struct ShareWorker
auto newsig = sig;
newsig.remove(i);
auto newval = val;
newval.bits().erase(newval.bits().begin() + i);
RTLIL::Const::Builder new_bits(val.size() - 1);
for (int j = 0; j < val.size(); ++j)
if (j != i)
new_bits.push_back(val[j]);
RTLIL::Const newval = new_bits.build();
db[newsig].insert(newval);
db[sig].erase(otherval);
@ -926,7 +930,8 @@ struct ShareWorker
if (used_in_a)
for (auto p : c_patterns) {
for (int i = 0; i < GetSize(sig_s); i++)
p.first.append(sig_s[i]), p.second.bits().push_back(RTLIL::State::S0);
p.first.append(sig_s[i]);
p.second.append(RTLIL::Const(RTLIL::State::S0, GetSize(sig_s)));
if (sort_check_activation_pattern(p))
if (!insert_capped(activation_patterns_cache[cell], p)) {
recursion_state.erase(cell);
@ -936,7 +941,8 @@ struct ShareWorker
for (int idx : used_in_b_parts)
for (auto p : c_patterns) {
p.first.append(sig_s[idx]), p.second.bits().push_back(RTLIL::State::S1);
p.first.append(sig_s[idx]);
p.second.append(RTLIL::Const(RTLIL::State::S1));
if (sort_check_activation_pattern(p))
if (!insert_capped(activation_patterns_cache[cell], p)) {
recursion_state.erase(cell);
@ -989,12 +995,14 @@ struct ShareWorker
{
std::vector<RTLIL::SigBit> p_first = p.first;
ssc_pair_t new_p;
RTLIL::Const::Builder new_p_second_bits;
for (int i = 0; i < GetSize(p_first); i++)
if (filter_bits.count(p_first[i]) == 0) {
new_p.first.append(p_first[i]);
new_p.second.bits().push_back(p.second.at(i));
new_p_second_bits.push_back(p.second.at(i));
}
new_p.second = new_p_second_bits.build();
out.insert(new_p);
}

4
passes/opt/wreduce.cc
View file

@ -220,10 +220,10 @@ struct WreduceWorker
// Narrow ARST_VALUE parameter to new size.
if (cell->parameters.count(ID::ARST_VALUE)) {
rst_value.bits().resize(GetSize(sig_q));
rst_value.resize(GetSize(sig_q), State::S0);
cell->setParam(ID::ARST_VALUE, rst_value);
} else if (cell->parameters.count(ID::SRST_VALUE)) {
rst_value.bits().resize(GetSize(sig_q));
rst_value.resize(GetSize(sig_q), State::S0);
cell->setParam(ID::SRST_VALUE, rst_value);
}

12
passes/proc/proc_init.cc
View file

@ -52,17 +52,15 @@ void proc_init(RTLIL::Module *mod, SigMap &sigmap, RTLIL::Process *proc)
Const value = valuesig.as_const();
Const &wireinit = lhs_c.wire->attributes[ID::init];
while (GetSize(wireinit) < lhs_c.wire->width)
wireinit.bits().push_back(State::Sx);
if (GetSize(wireinit) < lhs_c.wire->width)
wireinit.resize(lhs_c.wire->width, State::Sx);
for (int i = 0; i < lhs_c.width; i++) {
auto &initbit = wireinit.bits()[i + lhs_c.offset];
int index = i + lhs_c.offset;
State initbit = wireinit[index];
if (initbit != State::Sx && initbit != value[i])
log_cmd_error("Conflicting initialization values for %s.\n", log_signal(lhs_c));
initbit = value[i];
wireinit.set(index, value[i]);
}
log(" Set init value: %s = %s\n", log_signal(lhs_c.wire), log_signal(wireinit));
}
offset += lhs_c.width;

2
passes/proc/proc_memwr.cc
View file

@ -39,7 +39,7 @@ void proc_memwr(RTLIL::Module *mod, RTLIL::Process *proc, dict<IdString, int> &n
Const priority_mask(State::S0, port_id);
for (int i = 0; i < GetSize(prev_port_ids); i++)
if (memwr.priority_mask[i] == State::S1)
priority_mask.bits()[prev_port_ids[i]] = State::S1;
priority_mask.set(prev_port_ids[i], State::S1);
prev_port_ids.push_back(port_id);
RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($memwr_v2));

12
passes/proc/proc_rom.cc
View file

@ -97,7 +97,7 @@ struct RomWorker
log_debug("rejecting switch: lhs not uniform\n");
return;
}
val.bits()[it2->second] = it.second[i].data;
val.set(it2->second, it.second[i].data);
}
}
for (auto bit: val) {
@ -114,7 +114,7 @@ struct RomWorker
}
Const c = addr.as_const();
while (GetSize(c) && c.back() == State::S0)
c.bits().pop_back();
c.resize(c.size() - 1, State::S0);
if (GetSize(c) > swsigbits)
continue;
if (GetSize(c) > 30) {
@ -155,22 +155,22 @@ struct RomWorker
Mem mem(module, NEW_ID, GetSize(lhs), 0, 1 << abits);
mem.attributes = sw->attributes;
Const init_data;
Const::Builder builder(mem.size * GetSize(lhs));
for (int i = 0; i < mem.size; i++) {
auto it = vals.find(i);
if (it == vals.end()) {
log_assert(got_default);
for (auto bit: default_val)
init_data.bits().push_back(bit);
builder.push_back(bit);
} else {
for (auto bit: it->second)
init_data.bits().push_back(bit);
builder.push_back(bit);
}
}
MemInit init;
init.addr = 0;
init.data = init_data;
init.data = builder.build();
init.en = Const(State::S1, GetSize(lhs));
mem.inits.push_back(std::move(init));

4
passes/sat/eval.cc
View file

@ -256,7 +256,7 @@ struct VlogHammerReporter
for (int j = input_widths[i]-1; j >= 0; j--) {
ce.set(RTLIL::SigSpec(wire, j), bits.back());
recorded_set_vars.append(RTLIL::SigSpec(wire, j));
recorded_set_vals.bits().push_back(bits.back());
recorded_set_vars.append(RTLIL::Const(bits.back()));
bits.pop_back();
}
if (module == modules.front()) {
@ -346,7 +346,7 @@ struct VlogHammerReporter
log_error("Pattern %s is to short!\n", pattern.c_str());
patterns.push_back(sig.as_const());
if (invert_pattern) {
for (auto &bit : patterns.back().bits())
for (auto bit : patterns.back())
if (bit == RTLIL::State::S0)
bit = RTLIL::State::S1;
else if (bit == RTLIL::State::S1)

2
passes/sat/formalff.cc
View file

@ -851,7 +851,7 @@ struct FormalFfPass : public Pass {
auto before = ff.val_init;
for (int i = 0; i < ff.width; i++)
if (ff.val_init[i] == State::Sx && !worker.is_initval_used(ff.sig_q[i]))
ff.val_init.bits()[i] = State::S0;
ff.val_init.set(i, State::S0);
if (ff.val_init != before) {
log("Setting unused undefined initial value of %s.%s (%s) from %s to %s\n",

29
passes/sat/sat.cc
View file

@ -620,14 +620,18 @@ struct SatHelper
int last_timestep = -2;
for (auto &info : modelInfo)
{
RTLIL::Const value;
bool found_undef = false;
RTLIL::Const::Builder value_builder(info.width);
for (int i = 0; i < info.width; i++) {
value.bits().push_back(modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0);
if (enable_undef && modelValues.at(modelExpressions.size()/2 + info.offset + i))
value.bits().back() = RTLIL::State::Sx, found_undef = true;
RTLIL::State bit = modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0;
if (enable_undef && modelValues.at(modelExpressions.size()/2 + info.offset + i)) {
bit = RTLIL::State::Sx;
found_undef = true;
}
value_builder.push_back(bit);
}
RTLIL::Const value = value_builder.build();
if (info.timestep != last_timestep) {
const char *hline = "---------------------------------------------------------------------------------------------------"
@ -732,13 +736,14 @@ struct SatHelper
int last_timestep = -2;
for (auto &info : modelInfo)
{
RTLIL::Const value;
RTLIL::Const::Builder value_builder(info.width);
for (int i = 0; i < info.width; i++) {
value.bits().push_back(modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0);
RTLIL::State bit = modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0;
if (enable_undef && modelValues.at(modelExpressions.size()/2 + info.offset + i))
value.bits().back() = RTLIL::State::Sx;
bit = RTLIL::State::Sx;
value_builder.push_back(bit);
}
RTLIL::Const value = value_builder.build();
if (info.timestep != last_timestep) {
if(last_timestep == 0)
@ -779,12 +784,14 @@ struct SatHelper
for (auto &info : modelInfo)
{
Const value;
RTLIL::Const::Builder value_builder(info.width);
for (int i = 0; i < info.width; i++) {
value.bits().push_back(modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0);
RTLIL::State bit = modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0;
if (enable_undef && modelValues.at(modelExpressions.size()/2 + info.offset + i))
value.bits().back() = RTLIL::State::Sx;
bit = RTLIL::State::Sx;
value_builder.push_back(bit);
}
Const value = value_builder.build();
wavedata[info.description].first = info.width;
wavedata[info.description].second[info.timestep] = value;

32
passes/sat/sim.cc
View file

@ -127,16 +127,11 @@ struct SimShared
bool initstate = true;
};
void zinit(State &v)
{
if (v != State::S1)
v = State::S0;
}
void zinit(Const &v)
{
for (auto &bit : v.bits())
zinit(bit);
for (auto bit : v)
if (bit != State::S1)
bit = State::S0;
}
struct SimInstance
@ -419,16 +414,17 @@ struct SimInstance
Const get_state(SigSpec sig)
{
Const value;
Const::Builder builder(GetSize(sig));
for (auto bit : sigmap(sig))
if (bit.wire == nullptr)
value.bits().push_back(bit.data);
builder.push_back(bit.data);
else if (state_nets.count(bit))
value.bits().push_back(state_nets.at(bit));
builder.push_back(state_nets.at(bit));
else
value.bits().push_back(State::Sz);
builder.push_back(State::Sz);
Const value = builder.build();
if (shared->debug)
log("[%s] get %s: %s\n", hiername().c_str(), log_signal(sig), log_signal(value));
return value;
@ -488,7 +484,7 @@ struct SimInstance
for (int i = 0; i < GetSize(data); i++)
if (0 <= i+offset && i+offset < state.mem->size * state.mem->width && data[i] != State::Sa)
if (state.data[i+offset] != data[i])
dirty = true, state.data.bits()[i+offset] = data[i];
dirty = true, state.data.set(i+offset, data[i]);
if (dirty)
dirty_memories.insert(memid);
@ -500,7 +496,7 @@ struct SimInstance
if (offset >= state.mem->size * state.mem->width)
log_error("Addressing out of bounds bit %d/%d of memory %s\n", offset, state.mem->size * state.mem->width, log_id(memid));
if (state.data[offset] != data) {
state.data.bits()[offset] = data;
state.data.set(offset, data);
dirty_memories.insert(memid);
}
}
@ -717,10 +713,10 @@ struct SimInstance
for(int i=0;i<ff.past_d.size();i++) {
if (current_clr[i] == (ff_data.pol_clr ? State::S1 : State::S0)) {
current_q.bits()[i] = State::S0;
current_q.set(i, State::S0);
}
else if (current_set[i] == (ff_data.pol_set ? State::S1 : State::S0)) {
current_q.bits()[i] = State::S1;
current_q.set(i, State::S1);
}
}
}
@ -770,7 +766,7 @@ struct SimInstance
if (index >= 0 && index < mem.size)
for (int i = 0; i < (mem.width << port.wide_log2); i++)
if (enable[i] == State::S1 && mdb.data.at(index*mem.width+i) != data[i]) {
mdb.data.bits().at(index*mem.width+i) = data[i];
mdb.data.set(index*mem.width+i, data[i]);
dirty_memories.insert(mem.memid);
did_something = true;
}
@ -971,7 +967,7 @@ struct SimInstance
if (w->attributes.count(ID::init) == 0)
w->attributes[ID::init] = Const(State::Sx, GetSize(w));
w->attributes[ID::init].bits()[sig_q[i].offset] = initval[i];
w->attributes[ID::init].set(sig_q[i].offset, initval[i]);
}
}

11
passes/techmap/abc9_ops.cc
View file

@ -1216,7 +1216,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
auto Qi = initmap(Q);
auto it = Qi.wire->attributes.find(ID::init);
if (it != Qi.wire->attributes.end())
it->second.bits()[Qi.offset] = State::Sx;
it->second.set(Qi.offset, State::Sx);
}
else if (cell->type.in(ID($_AND_), ID($_NOT_)))
module->remove(cell);
@ -1526,8 +1526,11 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
log_assert(index < GetSize(A));
int i = 0;
while (i < GetSize(mask)) {
for (int j = 0; j < (1 << index); j++)
std::swap(mask.bits()[i+j], mask.bits()[i+j+(1 << index)]);
for (int j = 0; j < (1 << index); j++) {
State bit = mask[i+j];
mask.set(i+j, mask[i+j+(1 << index)]);
mask.set(i+j+(1 << index), bit);
}
i += 1 << (index+1);
}
A[index] = y_bit;
@ -1542,7 +1545,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
// and get cleaned away
clone_lut:
driver_mask = driver_lut->getParam(ID::LUT);
for (auto &b : driver_mask.bits()) {
for (auto b : driver_mask) {
if (b == RTLIL::State::S0) b = RTLIL::State::S1;
else if (b == RTLIL::State::S1) b = RTLIL::State::S0;
}

6
passes/techmap/dffinit.cc
View file

@ -118,13 +118,13 @@ struct DffinitPass : public Pass {
for (int i = 0; i < GetSize(sig); i++) {
if (initval[i] == State::Sx)
continue;
while (GetSize(value) <= i)
value.bits().push_back(State::S0);
if (GetSize(value) <= i)
value.resize(i + 1, State::S0);
if (noreinit && value[i] != State::Sx && value[i] != initval[i])
log_error("Trying to assign a different init value for %s.%s.%s which technically "
"have a conflicted init value.\n",
log_id(module), log_id(cell), log_id(it.second));
value.bits()[i] = initval[i];
value.set(i, initval[i]);
}
if (highlow_mode && GetSize(value) != 0) {

8
passes/techmap/dfflegalize.cc
View file

@ -869,17 +869,17 @@ struct DffLegalizePass : public Pass {
if (ff.has_arst) {
if (ff.val_arst[i] == State::Sx) {
if (!(supported & (mask << 8)))
ff.val_arst.bits()[i] = State::S0;
ff.val_arst.set(i, State::S0);
if (!(supported & (mask << 4)))
ff.val_arst.bits()[i] = State::S1;
ff.val_arst.set(i, State::S1);
}
}
if (ff.has_srst) {
if (ff.val_srst[i] == State::Sx) {
if (!(supported & (mask << 8)))
ff.val_srst.bits()[i] = State::S0;
ff.val_srst.set(i, State::S0);
if (!(supported & (mask << 4)))
ff.val_srst.bits()[i] = State::S1;
ff.val_srst.set(i, State::S1);
}
}
}

2
passes/techmap/flowmap.cc
View file

@ -1401,7 +1401,7 @@ struct FlowmapWorker
log_signal(node), log_signal(undef), env.c_str());
}
lut_table.bits()[i] = value.as_bool() ? State::S1 : State::S0;
lut_table.set(i, value.as_bool() ? State::S1 : State::S0);
ce.pop();
}

9
passes/techmap/techmap.cc
View file

@ -680,15 +680,16 @@ struct TechmapWorker
for (auto &conn : cell->connections())
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", log_id(conn.first))) != 0) {
RTLIL::Const value;
for (auto &bit : sigmap(conn.second)) {
SigSpec sm = sigmap(conn.second);
RTLIL::Const::Builder builder(GetSize(sm) * bits);
for (auto &bit : sm) {
int val = unique_bit_id.at(bit);
for (int i = 0; i < bits; i++) {
value.bits().push_back((val & 1) != 0 ? State::S1 : State::S0);
builder.push_back((val & 1) != 0 ? State::S1 : State::S0);
val = val >> 1;
}
}
parameters.emplace(stringf("\\_TECHMAP_CONNMAP_%s_", log_id(conn.first)), value);
parameters.emplace(stringf("\\_TECHMAP_CONNMAP_%s_", log_id(conn.first)), builder.build());
}
}

2
passes/techmap/zinit.cc
View file

@ -76,7 +76,7 @@ struct ZinitPass : public Pass {
if (ff.val_init[i] == State::S1)
bits.insert(i);
else if (ff.val_init[i] != State::S0 && all_mode)
ff.val_init.bits()[i] = State::S0;
ff.val_init.set(i, State::S0);
}
ff.flip_bits(bits);
ff.emit();

7
passes/tests/test_cell.cc
View file

@ -641,15 +641,16 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
if (!gold_wire->port_input)
continue;
RTLIL::Const in_value;
RTLIL::Const::Builder in_value_builder(GetSize(gold_wire));
for (int i = 0; i < GetSize(gold_wire); i++)
in_value.bits().push_back(xorshift32(2) ? State::S1 : State::S0);
in_value_builder.push_back(xorshift32(2) ? State::S1 : State::S0);
RTLIL::Const in_value = in_value_builder.build();
if (xorshift32(4) == 0) {
int inv_chance = 1 + xorshift32(8);
for (int i = 0; i < GetSize(gold_wire); i++)
if (xorshift32(inv_chance) == 0)
in_value.bits()[i] = RTLIL::Sx;
in_value.set(i, RTLIL::Sx);
}
if (verbose)