mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-11 00:23:26 +00:00
Code Activity

Merge pull request #2170 from boqwxp/cutpoint-efficiency

Browse source 
cutpoint: Improve efficiency by iterating over module ports instead of module wires
This commit is contained in:
whitequark 2020-06-19 01:13:19 +00:00 • committed by GitHub
commit b3b9f1bf2e
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
1 changed files with 10 additions and 9 deletions
Download patch file Download diff file Expand all files Collapse all files

19
passes/sat/cutpoint.cc
View file

@ -126,15 +126,16 @@ struct CutpointPass : public Pass {
} }
vector<Wire*> rewrite_wires; vector<Wire*> rewrite_wires;
for (auto wire : module->wires()) { for (auto id : module->ports) {
if (!wire->port_input) RTLIL::Wire *wire = module->wire(id);
continue; if (wire->port_input) {
int bit_count = 0; int bit_count = 0;
for (auto &bit : sigmap(wire)) for (auto &bit : sigmap(wire))
if (cutpoint_bits.count(bit)) if (cutpoint_bits.count(bit))
bit_count++; bit_count++;
if (bit_count) if (bit_count)
rewrite_wires.push_back(wire); rewrite_wires.push_back(wire);
}
} }
for (auto wire : rewrite_wires) { for (auto wire : rewrite_wires) {