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Fixup level policy.

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nella 2026-06-18 18:00:51 +02:00
parent 32a268d745
commit b3b1394cf1
15 changed files with 55 additions and 55 deletions
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4
tests/proc/proc_latches.ys
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@ -10,14 +10,14 @@ logger -check-expected
design -reset
# auto
# info
read_verilog <<EOT
module top(input g, rn, d, output reg q);
always @* if (~rn) q <= 0; else if (g) q <= d;
endmodule
EOT
logger -expect-no-warnings
proc -latches auto
proc -latches info
logger -check-expected
design -reset