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https://github.com/YosysHQ/yosys
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Merge pull request #1874 from boqwxp/cleanup_show
Clean up `passes/cmds/show.cc`.
This commit is contained in:
whitequark
GitHub
commit
b350398c04
1 changed files with 42 additions and 52 deletions
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@ -41,8 +41,6 @@
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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using RTLIL::id2cstr;
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#undef CLUSTER_CELLS_AND_PORTBOXES
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struct ShowWorker
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@ -101,7 +99,7 @@ struct ShowWorker
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{
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sig.sort_and_unify();
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for (auto &c : sig.chunks()) {
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if (c.wire != NULL)
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if (c.wire != nullptr)
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for (auto &s : color_selections)
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if (s.second.selected_members.count(module->name) > 0 && s.second.selected_members.at(module->name).count(c.wire->name) > 0)
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return stringf("color=\"%s\"", s.first.c_str());
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@ -218,7 +216,7 @@ struct ShowWorker
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if (sig.is_chunk()) {
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const RTLIL::SigChunk &c = sig.as_chunk();
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if (c.wire != NULL && design->selected_member(module->name, c.wire->name)) {
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if (c.wire != nullptr && design->selected_member(module->name, c.wire->name)) {
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if (!range_check || c.wire->width == c.width)
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return stringf("n%d", id2num(c.wire->name));
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} else {
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@ -230,7 +228,7 @@ struct ShowWorker
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return std::string();
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}
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std::string gen_portbox(std::string port, RTLIL::SigSpec sig, bool driver, std::string *node = NULL)
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std::string gen_portbox(std::string port, RTLIL::SigSpec sig, bool driver, std::string *node = nullptr)
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{
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std::string code;
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std::string net = gen_signode_simple(sig);
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@ -287,7 +285,7 @@ struct ShowWorker
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else
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code += stringf("x%d:e -> %s:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", idx, port.c_str(), nextColor(sig).c_str(), widthLabel(sig.size()).c_str());
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}
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if (node != NULL)
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if (node != nullptr)
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*node = stringf("x%d", idx);
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}
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else
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@ -300,7 +298,7 @@ struct ShowWorker
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net_conn_map[net].bits = sig.size();
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net_conn_map[net].color = nextColor(sig, net_conn_map[net].color);
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}
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if (node != NULL)
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if (node != nullptr)
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*node = net;
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}
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return code;
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@ -366,22 +364,20 @@ struct ShowWorker
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std::set<std::string> all_sources, all_sinks;
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std::map<std::string, std::string> wires_on_demand;
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for (auto &it : module->wires_) {
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if (!design->selected_member(module->name, it.first))
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continue;
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for (auto wire : module->selected_wires()) {
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const char *shape = "diamond";
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if (it.second->port_input || it.second->port_output)
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if (wire->port_input || wire->port_output)
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shape = "octagon";
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if (it.first[0] == '\\') {
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if (wire->name[0] == '\\') {
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fprintf(f, "n%d [ shape=%s, label=\"%s\", %s, fontcolor=\"black\" ];\n",
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id2num(it.first), shape, findLabel(it.first.str()),
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nextColor(RTLIL::SigSpec(it.second), "color=\"black\"").c_str());
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if (it.second->port_input)
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all_sources.insert(stringf("n%d", id2num(it.first)));
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else if (it.second->port_output)
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all_sinks.insert(stringf("n%d", id2num(it.first)));
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id2num(wire->name), shape, findLabel(wire->name.str()),
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nextColor(RTLIL::SigSpec(wire), "color=\"black\"").c_str());
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if (wire->port_input)
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all_sources.insert(stringf("n%d", id2num(wire->name)));
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else if (wire->port_output)
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all_sinks.insert(stringf("n%d", id2num(wire->name)));
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} else {
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wires_on_demand[stringf("n%d", id2num(it.first))] = it.first.str();
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wires_on_demand[stringf("n%d", id2num(wire->name))] = wire->name.str();
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}
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}
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@ -398,15 +394,12 @@ struct ShowWorker
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fprintf(f, "}\n");
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}
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for (auto &it : module->cells_)
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for (auto cell : module->selected_cells())
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{
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if (!design->selected_member(module->name, it.first))
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continue;
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std::vector<RTLIL::IdString> in_ports, out_ports;
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for (auto &conn : it.second->connections()) {
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if (!ct.cell_output(it.second->type, conn.first))
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for (auto &conn : cell->connections()) {
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if (!ct.cell_output(cell->type, conn.first))
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in_ports.push_back(conn.first);
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else
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out_ports.push_back(conn.first);
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@ -419,12 +412,12 @@ struct ShowWorker
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for (auto &p : in_ports)
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label_string += stringf("<p%d> %s%s|", id2num(p), escape(p.str()),
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genSignedLabels && it.second->hasParam(p.str() + "_SIGNED") &&
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it.second->getParam(p.str() + "_SIGNED").as_bool() ? "*" : "");
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genSignedLabels && cell->hasParam(p.str() + "_SIGNED") &&
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cell->getParam(p.str() + "_SIGNED").as_bool() ? "*" : "");
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if (label_string[label_string.size()-1] == '|')
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label_string = label_string.substr(0, label_string.size()-1);
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label_string += stringf("}|%s\\n%s|{", findLabel(it.first.str()), escape(it.second->type.str()));
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label_string += stringf("}|%s\\n%s|{", findLabel(cell->name.str()), escape(cell->type.str()));
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for (auto &p : out_ports)
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label_string += stringf("<p%d> %s|", id2num(p), escape(p.str()));
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@ -434,19 +427,19 @@ struct ShowWorker
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label_string += "}}";
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std::string code;
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for (auto &conn : it.second->connections()) {
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code += gen_portbox(stringf("c%d:p%d", id2num(it.first), id2num(conn.first)),
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conn.second, ct.cell_output(it.second->type, conn.first));
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for (auto &conn : cell->connections()) {
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code += gen_portbox(stringf("c%d:p%d", id2num(cell->name), id2num(conn.first)),
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conn.second, ct.cell_output(cell->type, conn.first));
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}
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#ifdef CLUSTER_CELLS_AND_PORTBOXES
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if (!code.empty())
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fprintf(f, "subgraph cluster_c%d {\nc%d [ shape=record, label=\"%s\"%s ];\n%s}\n",
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id2num(it.first), id2num(it.first), label_string.c_str(), findColor(it.first), code.c_str());
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id2num(cell->name), id2num(cell->name), label_string.c_str(), findColor(cell->name), code.c_str());
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else
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#endif
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fprintf(f, "c%d [ shape=record, label=\"%s\"%s ];\n%s",
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id2num(it.first), label_string.c_str(), findColor(it.first.str()), code.c_str());
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id2num(cell->name), label_string.c_str(), findColor(cell->name.str()), code.c_str());
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}
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for (auto &it : module->processes)
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@ -491,12 +484,12 @@ struct ShowWorker
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{
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bool found_lhs_wire = false;
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for (auto &c : conn.first.chunks()) {
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if (c.wire == NULL || design->selected_member(module->name, c.wire->name))
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if (c.wire == nullptr || design->selected_member(module->name, c.wire->name))
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found_lhs_wire = true;
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}
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bool found_rhs_wire = false;
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for (auto &c : conn.second.chunks()) {
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if (c.wire == NULL || design->selected_member(module->name, c.wire->name))
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if (c.wire == nullptr || design->selected_member(module->name, c.wire->name))
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found_rhs_wire = true;
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}
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if (!found_lhs_wire || !found_rhs_wire)
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@ -572,23 +565,21 @@ struct ShowWorker
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design->optimize();
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page_counter = 0;
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for (auto &mod_it : design->modules_)
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for (auto mod : design->selected_modules())
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{
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module = mod_it.second;
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if (!design->selected_module(module->name))
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continue;
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module = mod;
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if (design->selected_whole_module(module->name)) {
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if (module->get_blackbox_attribute()) {
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// log("Skipping blackbox module %s.\n", id2cstr(module->name));
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// log("Skipping blackbox module %s.\n", log_id(module->name));
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continue;
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} else
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if (module->cells_.empty() && module->connections().empty() && module->processes.empty()) {
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log("Skipping empty module %s.\n", id2cstr(module->name));
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if (module->cells().size() == 0 && module->connections().empty() && module->processes.empty()) {
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log("Skipping empty module %s.\n", log_id(module->name));
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continue;
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} else
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log("Dumping module %s to page %d.\n", id2cstr(module->name), ++page_counter);
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log("Dumping module %s to page %d.\n", log_id(module->name), ++page_counter);
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} else
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log("Dumping selected parts of module %s to page %d.\n", id2cstr(module->name), ++page_counter);
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log("Dumping selected parts of module %s to page %d.\n", log_id(module->name), ++page_counter);
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handle_module();
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}
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}
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@ -802,13 +793,12 @@ struct ShowPass : public Pass {
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if (format != "ps" && format != "dot") {
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int modcount = 0;
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for (auto &mod_it : design->modules_) {
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if (mod_it.second->get_blackbox_attribute())
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for (auto module : design->selected_modules()) {
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if (module->get_blackbox_attribute())
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continue;
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if (mod_it.second->cells_.empty() && mod_it.second->connections().empty())
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if (module->cells().size() == 0 && module->connections().empty())
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continue;
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if (design->selected_module(mod_it.first))
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modcount++;
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modcount++;
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}
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if (modcount > 1)
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log_cmd_error("For formats different than 'ps' or 'dot' only one module must be selected.\n");
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@ -835,7 +825,7 @@ struct ShowPass : public Pass {
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FILE *f = fopen(dot_file.c_str(), "w");
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if (custom_prefix)
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yosys_output_files.insert(dot_file);
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if (f == NULL) {
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if (f == nullptr) {
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for (auto lib : libs)
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delete lib;
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log_cmd_error("Can't open dot file `%s' for writing.\n", dot_file.c_str());
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@ -889,8 +879,8 @@ struct ShowPass : public Pass {
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if (flag_pause) {
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#ifdef YOSYS_ENABLE_READLINE
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char *input = NULL;
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while ((input = readline("Press ENTER to continue (or type 'shell' to open a shell)> ")) != NULL) {
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char *input = nullptr;
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while ((input = readline("Press ENTER to continue (or type 'shell' to open a shell)> ")) != nullptr) {
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if (input[strspn(input, " \t\r\n")] == 0)
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break;
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char *p = input + strspn(input, " \t\r\n");
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