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Merge pull request #1874 from boqwxp/cleanup_show

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Clean up `passes/cmds/show.cc`.
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whitequark 2020-04-06 18:32:20 +00:00 • committed by GitHub
commit b350398c04
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1 changed files with 42 additions and 52 deletions
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92
passes/cmds/show.cc
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@ -41,8 +41,6 @@
USING_YOSYS_NAMESPACE USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN PRIVATE_NAMESPACE_BEGIN
using RTLIL::id2cstr;
#undef CLUSTER_CELLS_AND_PORTBOXES #undef CLUSTER_CELLS_AND_PORTBOXES
struct ShowWorker struct ShowWorker
@ -101,7 +99,7 @@ struct ShowWorker
{ {
sig.sort_and_unify(); sig.sort_and_unify();
for (auto &c : sig.chunks()) { for (auto &c : sig.chunks()) {
if (c.wire != NULL) if (c.wire != nullptr)
for (auto &s : color_selections) for (auto &s : color_selections)
if (s.second.selected_members.count(module->name) > 0 && s.second.selected_members.at(module->name).count(c.wire->name) > 0) if (s.second.selected_members.count(module->name) > 0 && s.second.selected_members.at(module->name).count(c.wire->name) > 0)
return stringf("color=\"%s\"", s.first.c_str()); return stringf("color=\"%s\"", s.first.c_str());
@ -218,7 +216,7 @@ struct ShowWorker
if (sig.is_chunk()) { if (sig.is_chunk()) {
const RTLIL::SigChunk &c = sig.as_chunk(); const RTLIL::SigChunk &c = sig.as_chunk();
if (c.wire != NULL && design->selected_member(module->name, c.wire->name)) { if (c.wire != nullptr && design->selected_member(module->name, c.wire->name)) {
if (!range_check || c.wire->width == c.width) if (!range_check || c.wire->width == c.width)
return stringf("n%d", id2num(c.wire->name)); return stringf("n%d", id2num(c.wire->name));
} else { } else {
@ -230,7 +228,7 @@ struct ShowWorker
return std::string(); return std::string();
} }
std::string gen_portbox(std::string port, RTLIL::SigSpec sig, bool driver, std::string *node = NULL) std::string gen_portbox(std::string port, RTLIL::SigSpec sig, bool driver, std::string *node = nullptr)
{ {
std::string code; std::string code;
std::string net = gen_signode_simple(sig); std::string net = gen_signode_simple(sig);
@ -287,7 +285,7 @@ struct ShowWorker
else else
code += stringf("x%d:e -> %s:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", idx, port.c_str(), nextColor(sig).c_str(), widthLabel(sig.size()).c_str()); code += stringf("x%d:e -> %s:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", idx, port.c_str(), nextColor(sig).c_str(), widthLabel(sig.size()).c_str());
} }
if (node != NULL) if (node != nullptr)
*node = stringf("x%d", idx); *node = stringf("x%d", idx);
} }
else else
@ -300,7 +298,7 @@ struct ShowWorker
net_conn_map[net].bits = sig.size(); net_conn_map[net].bits = sig.size();
net_conn_map[net].color = nextColor(sig, net_conn_map[net].color); net_conn_map[net].color = nextColor(sig, net_conn_map[net].color);
} }
if (node != NULL) if (node != nullptr)
*node = net; *node = net;
} }
return code; return code;
@ -366,22 +364,20 @@ struct ShowWorker
std::set<std::string> all_sources, all_sinks; std::set<std::string> all_sources, all_sinks;
std::map<std::string, std::string> wires_on_demand; std::map<std::string, std::string> wires_on_demand;
for (auto &it : module->wires_) { for (auto wire : module->selected_wires()) {
if (!design->selected_member(module->name, it.first))
continue;
const char *shape = "diamond"; const char *shape = "diamond";
if (it.second->port_input || it.second->port_output) if (wire->port_input || wire->port_output)
shape = "octagon"; shape = "octagon";
if (it.first[0] == '\\') { if (wire->name[0] == '\\') {
fprintf(f, "n%d [ shape=%s, label=\"%s\", %s, fontcolor=\"black\" ];\n", fprintf(f, "n%d [ shape=%s, label=\"%s\", %s, fontcolor=\"black\" ];\n",
id2num(it.first), shape, findLabel(it.first.str()), id2num(wire->name), shape, findLabel(wire->name.str()),
nextColor(RTLIL::SigSpec(it.second), "color=\"black\"").c_str()); nextColor(RTLIL::SigSpec(wire), "color=\"black\"").c_str());
if (it.second->port_input) if (wire->port_input)
all_sources.insert(stringf("n%d", id2num(it.first))); all_sources.insert(stringf("n%d", id2num(wire->name)));
else if (it.second->port_output) else if (wire->port_output)
all_sinks.insert(stringf("n%d", id2num(it.first))); all_sinks.insert(stringf("n%d", id2num(wire->name)));
} else { } else {
wires_on_demand[stringf("n%d", id2num(it.first))] = it.first.str(); wires_on_demand[stringf("n%d", id2num(wire->name))] = wire->name.str();
} }
} }
@ -398,15 +394,12 @@ struct ShowWorker
fprintf(f, "}\n"); fprintf(f, "}\n");
} }
for (auto &it : module->cells_) for (auto cell : module->selected_cells())
{ {
if (!design->selected_member(module->name, it.first))
continue;
std::vector<RTLIL::IdString> in_ports, out_ports; std::vector<RTLIL::IdString> in_ports, out_ports;
for (auto &conn : it.second->connections()) { for (auto &conn : cell->connections()) {
if (!ct.cell_output(it.second->type, conn.first)) if (!ct.cell_output(cell->type, conn.first))
in_ports.push_back(conn.first); in_ports.push_back(conn.first);
else else
out_ports.push_back(conn.first); out_ports.push_back(conn.first);
@ -419,12 +412,12 @@ struct ShowWorker
for (auto &p : in_ports) for (auto &p : in_ports)
label_string += stringf("<p%d> %s%s|", id2num(p), escape(p.str()), label_string += stringf("<p%d> %s%s|", id2num(p), escape(p.str()),
genSignedLabels && it.second->hasParam(p.str() + "_SIGNED") && genSignedLabels && cell->hasParam(p.str() + "_SIGNED") &&
it.second->getParam(p.str() + "_SIGNED").as_bool() ? "*" : ""); cell->getParam(p.str() + "_SIGNED").as_bool() ? "*" : "");
if (label_string[label_string.size()-1] == '|') if (label_string[label_string.size()-1] == '|')
label_string = label_string.substr(0, label_string.size()-1); label_string = label_string.substr(0, label_string.size()-1);
label_string += stringf("}|%s\\n%s|{", findLabel(it.first.str()), escape(it.second->type.str())); label_string += stringf("}|%s\\n%s|{", findLabel(cell->name.str()), escape(cell->type.str()));
for (auto &p : out_ports) for (auto &p : out_ports)
label_string += stringf("<p%d> %s|", id2num(p), escape(p.str())); label_string += stringf("<p%d> %s|", id2num(p), escape(p.str()));
@ -434,19 +427,19 @@ struct ShowWorker
label_string += "}}"; label_string += "}}";
std::string code; std::string code;
for (auto &conn : it.second->connections()) { for (auto &conn : cell->connections()) {
code += gen_portbox(stringf("c%d:p%d", id2num(it.first), id2num(conn.first)), code += gen_portbox(stringf("c%d:p%d", id2num(cell->name), id2num(conn.first)),
conn.second, ct.cell_output(it.second->type, conn.first)); conn.second, ct.cell_output(cell->type, conn.first));
} }
#ifdef CLUSTER_CELLS_AND_PORTBOXES #ifdef CLUSTER_CELLS_AND_PORTBOXES
if (!code.empty()) if (!code.empty())
fprintf(f, "subgraph cluster_c%d {\nc%d [ shape=record, label=\"%s\"%s ];\n%s}\n", fprintf(f, "subgraph cluster_c%d {\nc%d [ shape=record, label=\"%s\"%s ];\n%s}\n",
id2num(it.first), id2num(it.first), label_string.c_str(), findColor(it.first), code.c_str()); id2num(cell->name), id2num(cell->name), label_string.c_str(), findColor(cell->name), code.c_str());
else else
#endif #endif
fprintf(f, "c%d [ shape=record, label=\"%s\"%s ];\n%s", fprintf(f, "c%d [ shape=record, label=\"%s\"%s ];\n%s",
id2num(it.first), label_string.c_str(), findColor(it.first.str()), code.c_str()); id2num(cell->name), label_string.c_str(), findColor(cell->name.str()), code.c_str());
} }
for (auto &it : module->processes) for (auto &it : module->processes)
@ -491,12 +484,12 @@ struct ShowWorker
{ {
bool found_lhs_wire = false; bool found_lhs_wire = false;
for (auto &c : conn.first.chunks()) { for (auto &c : conn.first.chunks()) {
if (c.wire == NULL || design->selected_member(module->name, c.wire->name)) if (c.wire == nullptr || design->selected_member(module->name, c.wire->name))
found_lhs_wire = true; found_lhs_wire = true;
} }
bool found_rhs_wire = false; bool found_rhs_wire = false;
for (auto &c : conn.second.chunks()) { for (auto &c : conn.second.chunks()) {
if (c.wire == NULL || design->selected_member(module->name, c.wire->name)) if (c.wire == nullptr || design->selected_member(module->name, c.wire->name))
found_rhs_wire = true; found_rhs_wire = true;
} }
if (!found_lhs_wire || !found_rhs_wire) if (!found_lhs_wire || !found_rhs_wire)
@ -572,23 +565,21 @@ struct ShowWorker
design->optimize(); design->optimize();
page_counter = 0; page_counter = 0;
for (auto &mod_it : design->modules_) for (auto mod : design->selected_modules())
{ {
module = mod_it.second; module = mod;
if (!design->selected_module(module->name))
continue;
if (design->selected_whole_module(module->name)) { if (design->selected_whole_module(module->name)) {
if (module->get_blackbox_attribute()) { if (module->get_blackbox_attribute()) {
// log("Skipping blackbox module %s.\n", id2cstr(module->name)); // log("Skipping blackbox module %s.\n", log_id(module->name));
continue; continue;
} else } else
if (module->cells_.empty() && module->connections().empty() && module->processes.empty()) { if (module->cells().size() == 0 && module->connections().empty() && module->processes.empty()) {
log("Skipping empty module %s.\n", id2cstr(module->name)); log("Skipping empty module %s.\n", log_id(module->name));
continue; continue;
} else } else
log("Dumping module %s to page %d.\n", id2cstr(module->name), ++page_counter); log("Dumping module %s to page %d.\n", log_id(module->name), ++page_counter);
} else } else
log("Dumping selected parts of module %s to page %d.\n", id2cstr(module->name), ++page_counter); log("Dumping selected parts of module %s to page %d.\n", log_id(module->name), ++page_counter);
handle_module(); handle_module();
} }
} }
@ -802,12 +793,11 @@ struct ShowPass : public Pass {
if (format != "ps" && format != "dot") { if (format != "ps" && format != "dot") {
int modcount = 0; int modcount = 0;
for (auto &mod_it : design->modules_) { for (auto module : design->selected_modules()) {
if (mod_it.second->get_blackbox_attribute()) if (module->get_blackbox_attribute())
continue; continue;
if (mod_it.second->cells_.empty() && mod_it.second->connections().empty()) if (module->cells().size() == 0 && module->connections().empty())
continue; continue;
if (design->selected_module(mod_it.first))
modcount++; modcount++;
} }
if (modcount > 1) if (modcount > 1)
@ -835,7 +825,7 @@ struct ShowPass : public Pass {
FILE *f = fopen(dot_file.c_str(), "w"); FILE *f = fopen(dot_file.c_str(), "w");
if (custom_prefix) if (custom_prefix)
yosys_output_files.insert(dot_file); yosys_output_files.insert(dot_file);
if (f == NULL) { if (f == nullptr) {
for (auto lib : libs) for (auto lib : libs)
delete lib; delete lib;
log_cmd_error("Can't open dot file `%s' for writing.\n", dot_file.c_str()); log_cmd_error("Can't open dot file `%s' for writing.\n", dot_file.c_str());
@ -889,8 +879,8 @@ struct ShowPass : public Pass {
if (flag_pause) { if (flag_pause) {
#ifdef YOSYS_ENABLE_READLINE #ifdef YOSYS_ENABLE_READLINE
char *input = NULL; char *input = nullptr;
while ((input = readline("Press ENTER to continue (or type 'shell' to open a shell)> ")) != NULL) { while ((input = readline("Press ENTER to continue (or type 'shell' to open a shell)> ")) != nullptr) {
if (input[strspn(input, " \t\r\n")] == 0) if (input[strspn(input, " \t\r\n")] == 0)
break; break;
char *p = input + strspn(input, " \t\r\n"); char *p = input + strspn(input, " \t\r\n");