mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-20 10:10:23 +00:00
Code Activity

Completed ngspice digital example with verilog tb

Browse source
This commit is contained in:
Uros Platise 2016-03-05 08:34:05 +01:00
parent b0ac32bc03
commit b34385ec92
5 changed files with 76 additions and 9 deletions
Download patch file Download diff file Expand all files Collapse all files

9
examples/cmos/testbench_digital.sp
View file

@ -1,13 +1,4 @@
* supply voltages
.global Vss Vdd
Vss Vss 0 DC 0
Vdd Vdd 0 DC 3
* simple transistor model
.MODEL cmosn NMOS LEVEL=1 VT0=0.7 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7
.MODEL cmosp PMOS LEVEL=1 VT0=-0.7 KP=50U GAMMA=0.57 LAMBDA=0.05 PHI=0.8
* load design and library
.include cmos_cells_digital.sp
.include synth.sp