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Completed ngspice digital example with verilog tb

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Uros Platise 2016-03-05 08:34:05 +01:00
parent b0ac32bc03
commit b34385ec92
5 changed files with 76 additions and 9 deletions
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examples/cmos/counter_digital.ys Normal file
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read_verilog counter.v
read_verilog -lib cmos_cells.v
proc;; memory;; techmap;;
dfflibmap -liberty cmos_cells.lib
abc -liberty cmos_cells.lib;;
# http://vlsiarch.ecen.okstate.edu/flows/MOSIS_SCMOS/latest/cadence/lib/tsmc025/signalstorm/osu025_stdcells.lib
# dfflibmap -liberty osu025_stdcells.lib
# abc -liberty osu025_stdcells.lib;;
write_verilog synth.v
write_spice -neg 0s -pos 1s synth.sp