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Move dsp_map.v into cells_map.v; cleanup synth_xilinx a little

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This commit is contained in:
Eddie Hung 2019-07-10 16:00:03 -07:00
parent cea7441d8a
commit b33ecd2a74
4 changed files with 42 additions and 45 deletions
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1
techlibs/xilinx/Makefile.inc
View file

@ -31,7 +31,6 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/dsp_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.box))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.lut))

41
techlibs/xilinx/cells_map.v
View file

@ -365,3 +365,44 @@ module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1);
MUXF8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O));
endmodule
`endif
module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] OUT);
wire [47:0] P_48;
DSP48E1 #(
// Disable all registers
.ACASCREG(0),
.ADREG(0),
.A_INPUT("DIRECT"),
.ALUMODEREG(0),
.AREG(0),
.BCASCREG(0),
.B_INPUT("DIRECT"),
.BREG(0),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(0),
.INMODEREG(0),
.MREG(0),
.OPMODEREG(0),
.PREG(0)
) _TECHMAP_REPLACE_ (
//Data path
.A({5'b0, A}),
.B(B),
.C(48'b0),
.D(24'b0),
.P(P_48),
.INMODE(4'b0000),
.ALUMODE(4'b0000),
.OPMODE(7'b000101),
.CARRYINSEL(3'b000),
.ACIN(30'b0),
.BCIN(18'b0),
.PCIN(48'b0),
.CARRYIN(1'b0)
);
assign OUT = P_48;
endmodule

40
techlibs/xilinx/dsp_map.v
View file

@ -1,40 +0,0 @@
module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] OUT);
wire [47:0] P_48;
DSP48E1 #(
// Disable all registers
.ACASCREG(0),
.ADREG(0),
.A_INPUT("DIRECT"),
.ALUMODEREG(0),
.AREG(0),
.BCASCREG(0),
.B_INPUT("DIRECT"),
.BREG(0),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(0),
.INMODEREG(0),
.MREG(0),
.OPMODEREG(0),
.PREG(0)
) _TECHMAP_REPLACE_ (
//Data path
.A({5'b0, A}),
.B(B),
.C(48'b0),
.D(24'b0),
.P(P_48),
.INMODE(4'b0000),
.ALUMODE(4'b0000),
.OPMODE(7'b000101),
.CARRYINSEL(3'b000),
.ACIN(30'b0),
.BCIN(18'b0),
.PCIN(48'b0),
.CARRYIN(1'b0)
);
assign OUT = P_48;
endmodule

5
techlibs/xilinx/synth_xilinx.cc
View file

@ -279,11 +279,8 @@ struct SynthXilinxPass : public ScriptPass
run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6");
if (!nodsp || help_mode) {
if (!nodsp || help_mode)
run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 -D DSP_NAME=$__MUL25X18");
run("clean");
run("techmap -map +/xilinx/dsp_map.v");
}
run("alumacc");
run("share");