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Added examples/smtbmc

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This commit is contained in:
Clifford Wolf 2016-07-13 09:49:05 +02:00
parent 2afc72cae3
commit b3155af5f6
2 changed files with 30 additions and 0 deletions
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examples/smtbmc/Makefile Normal file
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demo1: demo1.smt2
yosys-smtbmc -c demo1.vcd demo1.smt2
yosys-smtbmc -i -c demo1.vcd demo1.smt2
demo1.smt2: demo1.v
yosys -p 'read_verilog -formal demo1.v; prep -top demo1; write_smt2 -wires -mem -bv demo1.smt2'
clean:
rm -f demo1.smt2
.PHONY: demo1 clean

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examples/smtbmc/demo1.v Normal file
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module demo1(input clk, input addtwo, output iseven);
reg [3:0] cnt = 0;
wire [3:0] next_cnt;
inc inc_inst (addtwo, iseven, cnt, next_cnt);
always @(posedge clk)
cnt = (iseven ? cnt == 10 : cnt == 11) ? 0 : next_cnt;
assert property (cnt != 15);
// initial expect ((iseven && addtwo) || cnt == 9);
endmodule
module inc(input addtwo, output iseven, input [3:0] a, output [3:0] y);
assign iseven = !a[0];
assign y = a + (addtwo ? 2 : 1);
endmodule