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filterlib: prefer using precedence over unsynthesizable verilog

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This commit is contained in:
Emil J. Tywoniak 2025-11-21 00:43:54 +01:00
parent d5c1cd8fc0
commit b3112bf025
5 changed files with 235 additions and 76 deletions
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15
tests/liberty/unquoted.lib.verilogsim.ok
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@ -5,8 +5,11 @@ module dff1 (D, CLK, Q);
output Q;
assign Q = IQ; // IQ
always @(posedge CLK) begin
// !D
// (~D)
IQ <= (~D);
end
always @(posedge CLK) begin
// ~((~D))
IQN <= ~((~D));
end
endmodule
@ -17,8 +20,11 @@ module dff2 (D, CLK, Q);
output Q;
assign Q = IQ; // "IQ"
always @(posedge CLK) begin
// D '
// (~D)
IQ <= (~D);
end
always @(posedge CLK) begin
// ~((~D))
IQN <= ~((~D));
end
endmodule
@ -32,8 +38,11 @@ module dffe (D, EN, CLK, Q, QN);
output QN;
assign QN = IQN; // "IQN"
always @(negedge CLK) begin
// ( D & EN ) | ( IQ & ! EN )
// ((D&EN)|(IQ&(~EN)))
IQ <= ((D&EN)|(IQ&(~EN)));
end
always @(negedge CLK) begin
// ~(((D&EN)|(IQ&(~EN))))
IQN <= ~(((D&EN)|(IQ&(~EN))));
end
endmodule