mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-25 06:59:33 +00:00
Code Activity

filterlib: prefer using precedence over unsynthesizable verilog

Browse source
This commit is contained in:
Emil J. Tywoniak 2025-11-21 00:43:54 +01:00
parent d5c1cd8fc0
commit b3112bf025
5 changed files with 235 additions and 76 deletions
Download patch file Download diff file Expand all files Collapse all files

28
tests/liberty/normal.lib.verilogsim.ok
View file

@ -41,6 +41,7 @@ module imux2 (A, B, S, Y);
endmodule
module dff (D, CLK, RESET, PRESET, Q, QN);
reg IQ, IQN;
wire IQ_clear, IQ_preset;
input D;
input CLK;
input RESET;
@ -49,25 +50,32 @@ module dff (D, CLK, RESET, PRESET, Q, QN);
assign Q = IQ; // "IQ"
output QN;
assign QN = IQN; // "IQN"
always @(posedge CLK, posedge RESET, posedge PRESET) begin
if ((RESET) && (PRESET)) begin
always @(posedge CLK, posedge IQ_clear, posedge IQ_preset) begin
if (IQ_clear) begin
IQ <= 0;
IQN <= 0;
end
else if (RESET) begin
IQ <= 0;
IQN <= 1;
end
else if (PRESET) begin
else if (IQ_preset) begin
IQ <= 1;
IQN <= 0;
end
else begin
// "D"
// D
IQ <= D;
end
end
always @(posedge CLK, posedge IQ_clear, posedge IQ_preset) begin
if (IQ_preset) begin
IQN <= 0;
end
else if (IQ_clear) begin
IQN <= 1;
end
else begin
// ~(D)
IQN <= ~(D);
end
end
assign IQ_clear = RESET;
assign IQ_preset = PRESET;
endmodule
module latch (D, G, Q, QN);
reg IQ, IQN;