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filterlib: prefer using precedence over unsynthesizable verilog

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This commit is contained in:
Emil J. Tywoniak 2025-11-21 00:43:54 +01:00
parent d5c1cd8fc0
commit b3112bf025
5 changed files with 235 additions and 76 deletions
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5
tests/liberty/dff.lib.verilogsim.ok
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@ -5,8 +5,11 @@ module dff (D, CLK, Q);
output Q;
assign Q = IQ; // IQ
always @(posedge CLK) begin
// "(D)"
// D
IQ <= D;
end
always @(posedge CLK) begin
// ~(D)
IQN <= ~(D);
end
endmodule