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filterlib: prefer using precedence over unsynthesizable verilog

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This commit is contained in:
Emil J. Tywoniak 2025-11-21 00:43:54 +01:00
parent d5c1cd8fc0
commit b3112bf025
5 changed files with 235 additions and 76 deletions
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5
tests/liberty/dff.lib.verilogsim.ok
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@ -5,8 +5,11 @@ module dff (D, CLK, Q);
output Q;
assign Q = IQ; // IQ
always @(posedge CLK) begin
// "(D)"
// D
IQ <= D;
end
always @(posedge CLK) begin
// ~(D)
IQN <= ~(D);
end
endmodule

28
tests/liberty/normal.lib.verilogsim.ok
View file

@ -41,6 +41,7 @@ module imux2 (A, B, S, Y);
endmodule
module dff (D, CLK, RESET, PRESET, Q, QN);
reg IQ, IQN;
wire IQ_clear, IQ_preset;
input D;
input CLK;
input RESET;
@ -49,25 +50,32 @@ module dff (D, CLK, RESET, PRESET, Q, QN);
assign Q = IQ; // "IQ"
output QN;
assign QN = IQN; // "IQN"
always @(posedge CLK, posedge RESET, posedge PRESET) begin
if ((RESET) && (PRESET)) begin
always @(posedge CLK, posedge IQ_clear, posedge IQ_preset) begin
if (IQ_clear) begin
IQ <= 0;
IQN <= 0;
end
else if (RESET) begin
IQ <= 0;
IQN <= 1;
end
else if (PRESET) begin
else if (IQ_preset) begin
IQ <= 1;
IQN <= 0;
end
else begin
// "D"
// D
IQ <= D;
end
end
always @(posedge CLK, posedge IQ_clear, posedge IQ_preset) begin
if (IQ_preset) begin
IQN <= 0;
end
else if (IQ_clear) begin
IQN <= 1;
end
else begin
// ~(D)
IQN <= ~(D);
end
end
assign IQ_clear = RESET;
assign IQ_preset = PRESET;
endmodule
module latch (D, G, Q, QN);
reg IQ, IQN;

5
tests/liberty/semicolextra.lib.verilogsim.ok
View file

@ -4,8 +4,11 @@ module DFF (D, CK, Q);
input CK;
output Q;
always @(posedge CK) begin
// "D"
// D
IQ <= D;
end
always @(posedge CK) begin
// ~(D)
IQN <= ~(D);
end
endmodule

15
tests/liberty/unquoted.lib.verilogsim.ok
View file

@ -5,8 +5,11 @@ module dff1 (D, CLK, Q);
output Q;
assign Q = IQ; // IQ
always @(posedge CLK) begin
// !D
// (~D)
IQ <= (~D);
end
always @(posedge CLK) begin
// ~((~D))
IQN <= ~((~D));
end
endmodule
@ -17,8 +20,11 @@ module dff2 (D, CLK, Q);
output Q;
assign Q = IQ; // "IQ"
always @(posedge CLK) begin
// D '
// (~D)
IQ <= (~D);
end
always @(posedge CLK) begin
// ~((~D))
IQN <= ~((~D));
end
endmodule
@ -32,8 +38,11 @@ module dffe (D, EN, CLK, Q, QN);
output QN;
assign QN = IQN; // "IQN"
always @(negedge CLK) begin
// ( D & EN ) | ( IQ & ! EN )
// ((D&EN)|(IQ&(~EN)))
IQ <= ((D&EN)|(IQ&(~EN)));
end
always @(negedge CLK) begin
// ~(((D&EN)|(IQ&(~EN))))
IQN <= ~(((D&EN)|(IQ&(~EN))));
end
endmodule