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https://github.com/YosysHQ/yosys
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filterlib: prefer using precedence over unsynthesizable verilog
This commit is contained in:
Emil J. Tywoniak
parent
d5c1cd8fc0
commit
b3112bf025
5 changed files with 235 additions and 76 deletions
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@ -827,6 +827,17 @@ std::string vlog_identifier(std::string str)
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return str;
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}
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void event2vl_wire(std::string &edge, LibertyExpression& parsed, const std::string& wire)
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{
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edge.clear();
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if (parsed.kind == LibertyExpression::Kind::NOT) {
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edge = "negedge " + wire;
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// parsed = parsed.children[0];
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} else {
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edge = "posedge " + wire;
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}
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}
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void event2vl(const LibertyAst *ast, std::string &edge, std::string &expr)
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{
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edge.clear();
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@ -843,33 +854,160 @@ void event2vl(const LibertyAst *ast, std::string &edge, std::string &expr)
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}
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}
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void clear_preset_var(std::string var, std::string type)
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enum ClearPresetVar {
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Error,
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L,
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H,
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T,
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X,
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};
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ClearPresetVar clear_preset_var(std::string type)
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{
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if (type.find('L') != std::string::npos) {
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return ClearPresetVar::L;
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}
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if (type.find('H') != std::string::npos) {
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return ClearPresetVar::H;
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}
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if (type.find('T') != std::string::npos) {
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return ClearPresetVar::T;
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}
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if (type.find('X') != std::string::npos) {
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return ClearPresetVar::X;
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}
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return ClearPresetVar::X;
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}
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void print_clear_preset_var(std::string var, ClearPresetVar type)
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{
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if (type == ClearPresetVar::L) {
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printf(" %s <= 0;\n", var.c_str());
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return;
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}
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if (type.find('H') != std::string::npos) {
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if (type == ClearPresetVar::H) {
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printf(" %s <= 1;\n", var.c_str());
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return;
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}
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if (type.find('T') != std::string::npos) {
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if (type == ClearPresetVar::T) {
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printf(" %s <= ~%s;\n", var.c_str(), var.c_str());
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return;
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}
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if (type.find('X') != std::string::npos) {
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if (type == ClearPresetVar::X) {
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printf(" %s <= 'bx;\n", var.c_str());
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return;
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}
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}
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struct FfEdge {
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std::string edge;
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std::string expr;
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};
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struct FfEdges {
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FfEdge clock;
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FfEdge clear;
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FfEdge preset;
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std::string edge;
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void wired(FfEdge& edge, const LibertyAst* ast, const std::string& wire, const char* tag) {
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auto* found = ast->find(tag);
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if (!found)
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return;
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auto lexer = LibertyExpression::Lexer(found->value);
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auto expr = LibertyExpression::parse(lexer);
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event2vl_wire(edge.edge, expr, wire);
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edge.expr = expr.vlog_str();
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}
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FfEdges(LibertyAst* child, const std::string& clear_wire, const std::string& preset_wire) {
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wired(clear, child, clear_wire, "clear");
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wired(preset, child, preset_wire, "preset");
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event2vl(child->find("clocked_on"), clock.edge, clock.expr);
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edge = "";
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if (!clock.edge.empty())
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edge += (edge.empty() ? "" : ", ") + clock.edge;
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if (!clear.edge.empty())
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edge += (edge.empty() ? "" : ", ") + clear.edge;
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if (!preset.edge.empty())
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edge += (edge.empty() ? "" : ", ") + preset.edge;
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}
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};
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struct FfVar {
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std::string var;
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std::string edge;
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FfEdge clear;
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FfEdge preset;
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// Value for both asserted
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const char* clear_preset_var_name;
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std::string next_state;
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const char* else_prefix = "";
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public:
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void proc_header() {
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printf(" always @(%s) begin\n", edge.c_str());
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}
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void proc_footer() {
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if (*else_prefix)
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printf(" end\n");
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printf(" end\n");
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}
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void proc_cond(FfEdge& edge, const char* value) {
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printf(" %sif (%s) begin\n", else_prefix, edge.expr.c_str());
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printf(" %s <= %s;\n", var.c_str(), value);
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printf(" end\n");
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else_prefix = "else ";
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}
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void proc_cond_clear() { proc_cond(clear, "0"); }
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void proc_cond_preset() { proc_cond(preset, "1"); }
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void proc_next_state() {
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if (*else_prefix)
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printf(" %sbegin\n", else_prefix);
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printf(" %s <= %s;\n", var.c_str(), next_state.c_str());
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}
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void proc(LibertyAst* child) {
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else_prefix = "";
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proc_header();
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if (!clear.expr.empty() && !preset.expr.empty()) {
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ClearPresetVar clear_preset = clear_preset_var(find_non_null(child, clear_preset_var_name)->value);
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if (clear_preset == ClearPresetVar::L) {
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proc_cond_clear();
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proc_cond_preset();
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proc_next_state();
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proc_footer();
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return;
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} else if (clear_preset == ClearPresetVar::H) {
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// Notice that preset and clear are swapped
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proc_cond_preset();
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proc_cond_clear();
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proc_next_state();
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proc_footer();
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return;
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} else {
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// Boo, we have to emit non-synthesizable verilog
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printf(" %sif ((%s) && (%s)) begin\n", else_prefix, clear.expr.c_str(), preset.expr.c_str());
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print_clear_preset_var(var, clear_preset);
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printf(" end\n");
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else_prefix = "else ";
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}
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}
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if (!clear.expr.empty()) {
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proc_cond_clear();
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}
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if (!preset.expr.empty()) {
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proc_cond_preset();
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}
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proc_next_state();
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proc_footer();
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}
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};
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void gen_verilogsim_cell(const LibertyAst *ast)
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{
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if (ast->find("statetable") != NULL)
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return;
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CHECK_NV(ast->args.size(), == 1);
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printf("module %s (", vlog_identifier(ast->args[0]).c_str());
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auto module_name = vlog_identifier(ast->args[0]);
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printf("module %s (", module_name.c_str());
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bool first = true;
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for (auto child : ast->children) {
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if (child->id != "pin")
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@ -883,13 +1021,29 @@ void gen_verilogsim_cell(const LibertyAst *ast)
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for (auto child : ast->children) {
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if (child->id != "ff" && child->id != "latch")
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continue;
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printf(" reg ");
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first = true;
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std::string iq = "";
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for (auto arg : child->args) {
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if (first)
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printf(" reg ");
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printf("%s%s", first ? "" : ", ", vlog_identifier(arg).c_str());
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if (first)
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iq = vlog_identifier(arg);
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first = false;
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}
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printf(";\n");
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if (!first)
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printf(";\n");
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first = true;
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for (auto gchild : child->children) {
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if (gchild->id == "clear" || gchild->id == "preset") {
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if (first)
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printf(" wire ");
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printf("%s%s_%s", first ? "" : ", ", iq.c_str(), gchild->id.c_str());
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first = false;
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}
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}
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if (!first)
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printf(";\n");
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}
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for (auto child : ast->children) {
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@ -909,63 +1063,45 @@ void gen_verilogsim_cell(const LibertyAst *ast)
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if (child->id != "ff" || child->args.size() != 2)
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continue;
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std::string iq_var = vlog_identifier(child->args[0]);
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std::string iqn_var = vlog_identifier(child->args[1]);
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auto iq_name = vlog_identifier(child->args[0]);
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auto clear_wire = iq_name + "_clear";
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auto preset_wire = iq_name + "_preset";
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FfEdges edges(child, clear_wire, preset_wire);
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std::string clock_edge, clock_expr;
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event2vl(child->find("clocked_on"), clock_edge, clock_expr);
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std::string clear_edge, clear_expr;
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event2vl(child->find("clear"), clear_edge, clear_expr);
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std::string preset_edge, preset_expr;
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event2vl(child->find("preset"), preset_edge, preset_expr);
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std::string edge = "";
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if (!clock_edge.empty())
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edge += (edge.empty() ? "" : ", ") + clock_edge;
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if (!clear_edge.empty())
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edge += (edge.empty() ? "" : ", ") + clear_edge;
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if (!preset_edge.empty())
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edge += (edge.empty() ? "" : ", ") + preset_edge;
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if (edge.empty())
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if (edges.edge.empty())
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continue;
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printf(" always @(%s) begin\n", edge.c_str());
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std::string next_state = func2vl(find_non_null(child, "next_state")->value);
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std::string not_next_state = std::string("~(") + next_state + ")";
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const char *else_prefix = "";
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if (!clear_expr.empty() && !preset_expr.empty()) {
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printf(" %sif ((%s) && (%s)) begin\n", else_prefix, clear_expr.c_str(), preset_expr.c_str());
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clear_preset_var(iq_var, find_non_null(child, "clear_preset_var1")->value);
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clear_preset_var(iqn_var, find_non_null(child, "clear_preset_var2")->value);
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printf(" end\n");
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else_prefix = "else ";
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}
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if (!clear_expr.empty()) {
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printf(" %sif (%s) begin\n", else_prefix, clear_expr.c_str());
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printf(" %s <= 0;\n", iq_var.c_str());
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printf(" %s <= 1;\n", iqn_var.c_str());
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printf(" end\n");
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else_prefix = "else ";
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}
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if (!preset_expr.empty()) {
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printf(" %sif (%s) begin\n", else_prefix, preset_expr.c_str());
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printf(" %s <= 1;\n", iq_var.c_str());
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printf(" %s <= 0;\n", iqn_var.c_str());
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printf(" end\n");
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else_prefix = "else ";
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}
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if (*else_prefix)
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printf(" %sbegin\n", else_prefix);
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std::string expr = find_non_null(child, "next_state")->value;
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printf(" // %s\n", expr.c_str());
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printf(" %s <= %s;\n", iq_var.c_str(), func2vl(expr).c_str());
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printf(" %s <= ~(%s);\n", iqn_var.c_str(), func2vl(expr).c_str());
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if (*else_prefix)
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printf(" end\n");
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printf(" end\n");
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if (edges.clear.expr.length())
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std::swap(clear_wire, edges.clear.expr);
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if (edges.preset.expr.length())
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std::swap(preset_wire, edges.preset.expr);
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auto iq = FfVar {
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.var = vlog_identifier(child->args[0]),
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.edge = edges.edge,
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.clear = edges.clear,
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.preset = edges.preset,
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.clear_preset_var_name = "clear_preset_var1",
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.next_state = next_state,
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};
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auto iqn = FfVar {
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.var = vlog_identifier(child->args[1]),
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.edge = edges.edge,
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// Swapped clear and preset
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.clear = edges.preset,
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.preset = edges.clear,
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.clear_preset_var_name = "clear_preset_var2",
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.next_state = not_next_state,
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};
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iq.proc(child);
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iqn.proc(child);
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if (edges.clear.expr.length())
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printf(" assign %s = %s;\n", edges.clear.expr.c_str(), clear_wire.c_str());
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if (edges.preset.expr.length())
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printf(" assign %s = %s;\n", edges.preset.expr.c_str(), preset_wire.c_str());
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}
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for (auto child : ast->children)
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@ -990,8 +1126,8 @@ void gen_verilogsim_cell(const LibertyAst *ast)
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const char *else_prefix = "";
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if (!clear_expr.empty() && !preset_expr.empty()) {
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printf(" %sif ((%s) && (%s)) begin\n", else_prefix, clear_expr.c_str(), preset_expr.c_str());
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clear_preset_var(iq_var, find_non_null(child, "clear_preset_var1")->value);
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clear_preset_var(iqn_var, find_non_null(child, "clear_preset_var2")->value);
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print_clear_preset_var(iq_var, clear_preset_var(find_non_null(child, "clear_preset_var1")->value));
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print_clear_preset_var(iqn_var, clear_preset_var(find_non_null(child, "clear_preset_var2")->value));
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printf(" end\n");
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else_prefix = "else ";
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}
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