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Docs: Force read_verilog to avoid verific header

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Krystine Sherwin 2024-04-13 11:33:04 +12:00
parent 1d7b7ddfd7
commit b3024289c6
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1 changed files with 3 additions and 3 deletions
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6
docs/source/code_examples/extensions/Makefile
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@ -13,18 +13,18 @@ my_cmd.so: my_cmd.cc
$(YOSYS)-config --exec --cxx $(subst $(DATDIR),../../../../share,$(CXXFLAGS)) --ldflags -o my_cmd.so -shared my_cmd.cc --ldlibs $(YOSYS)-config --exec --cxx $(subst $(DATDIR),../../../../share,$(CXXFLAGS)) --ldflags -o my_cmd.so -shared my_cmd.cc --ldlibs
test0.log: my_cmd.so test0.log: my_cmd.so
$(YOSYS) -QTl test0.log_new -m ./my_cmd.so -p 'my_cmd foo bar' absval_ref.v $(YOSYS) -QTl test0.log_new -m ./my_cmd.so -p 'my_cmd foo bar' -f verilog absval_ref.v
mv test0.log_new test0.log mv test0.log_new test0.log
test1.log: my_cmd.so test1.log: my_cmd.so
$(YOSYS) -QTl test1.log_new -m ./my_cmd.so -p 'clean; test1; dump' absval_ref.v $(YOSYS) -QTl test1.log_new -m ./my_cmd.so -p 'clean; test1; dump' -f verilog absval_ref.v
mv test1.log_new test1.log mv test1.log_new test1.log
test1.dot: my_cmd.so test1.dot: my_cmd.so
$(YOSYS) -m ./my_cmd.so -p 'test1; show -format dot -prefix test1' $(YOSYS) -m ./my_cmd.so -p 'test1; show -format dot -prefix test1'
test2.log: my_cmd.so test2.log: my_cmd.so
$(YOSYS) -QTl test2.log_new -m ./my_cmd.so -p 'hierarchy -top test; test2' sigmap_test.v $(YOSYS) -QTl test2.log_new -m ./my_cmd.so -p 'hierarchy -top test; test2' -f verilog sigmap_test.v
mv test2.log_new test2.log mv test2.log_new test2.log
.PHONY: clean .PHONY: clean