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opt_dff: sigmap bits before looking up muxes

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This commit is contained in:
George Rennie 2024-11-28 18:36:59 +01:00
parent 6f3376cbe6
commit b30211c60a
1 changed files with 23 additions and 12 deletions
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35
passes/opt/opt_dff.cc
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@ -29,6 +29,7 @@
#include "passes/techmap/simplemap.h"
#include <stdio.h>
#include <stdlib.h>
#include <optional>
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
@ -95,6 +96,18 @@ struct OptDffWorker
}
// If this bit sigmaps to a bit driven by a mux ouput bit that only drives this
// bit, returns that mux otherwise nullopt
std::optional<cell_int_t> mergeable_mux(SigBit bit) {
sigmap.apply(bit);
auto it = bit2mux.find(bit);
if (it == bit2mux.end() || bitusers[bit] != 1)
return std::nullopt;
return it->second;
}
State combine_const(State a, State b) {
if (a == State::Sx && !opt.keepdc)
return b;
@ -591,13 +604,12 @@ struct OptDffWorker
State reset_val = State::Sx;
if (ff.has_srst)
reset_val = ff.val_srst[i];
while (bit2mux.count(ff.sig_d[i]) && bitusers[ff.sig_d[i]] == 1) {
cell_int_t mbit = bit2mux.at(ff.sig_d[i]);
if (GetSize(mbit.first->getPort(ID::S)) != 1)
while (const auto mbit = mergeable_mux(ff.sig_d[i])) {
if (GetSize(mbit->first->getPort(ID::S)) != 1)
break;
SigBit s = mbit.first->getPort(ID::S);
SigBit a = mbit.first->getPort(ID::A)[mbit.second];
SigBit b = mbit.first->getPort(ID::B)[mbit.second];
SigBit s = mbit->first->getPort(ID::S);
SigBit a = mbit->first->getPort(ID::A)[mbit->second];
SigBit b = mbit->first->getPort(ID::B)[mbit->second];
// Workaround for funny memory WE pattern.
if ((a == State::S0 || a == State::S1) && (b == State::S0 || b == State::S1))
break;
@ -668,13 +680,12 @@ struct OptDffWorker
for (int i = 0 ; i < ff.width; i++) {
// First, eat up as many simple muxes as possible.
ctrls_t enables;
while (bit2mux.count(ff.sig_d[i]) && bitusers[ff.sig_d[i]] == 1) {
cell_int_t mbit = bit2mux.at(ff.sig_d[i]);
if (GetSize(mbit.first->getPort(ID::S)) != 1)
while (const auto mbit = mergeable_mux(ff.sig_d[i])) {
if (GetSize(mbit->first->getPort(ID::S)) != 1)
break;
SigBit s = mbit.first->getPort(ID::S);
SigBit a = mbit.first->getPort(ID::A)[mbit.second];
SigBit b = mbit.first->getPort(ID::B)[mbit.second];
SigBit s = mbit->first->getPort(ID::S);
SigBit a = mbit->first->getPort(ID::A)[mbit->second];
SigBit b = mbit->first->getPort(ID::B)[mbit->second];
if (a == ff.sig_q[i]) {
enables.insert(ctrl_t(s, true));
ff.sig_d[i] = b;