3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-15 02:21:17 +00:00

dfflibmap: fix next_state inversion propagation for DFF flops by inverting reset value polarity

This commit is contained in:
Emil J. Tywoniak 2025-10-28 13:01:26 +01:00
parent 8bc63ef6da
commit b2fe335b2d
3 changed files with 62 additions and 0 deletions

View file

@ -108,6 +108,37 @@ copy top top_unmapped
simplemap top
dfflibmap -liberty dfflibmap_dffn_dffe.lib -liberty dfflibmap_dffsr_not_next.lib top
async2sync
flatten
opt_clean -purge
equiv_make top top_unmapped equiv
equiv_induct equiv
equiv_status -assert equiv
##################################################################
design -reset
read_verilog <<EOT
module top(input C, D, R, output Q);
// DFF with preset
always @(posedge C or negedge R) begin
if (!R) Q <= 1'b1;
else Q <= D;
end
endmodule
EOT
proc
opt
read_liberty dfflibmap_dffn_dffe.lib
read_liberty dfflibmap_dff_not_next.lib
copy top top_unmapped
simplemap top
dfflibmap -liberty dfflibmap_dffn_dffe.lib -liberty dfflibmap_dff_not_next.lib top
async2sync
flatten
opt_clean -purge