mirror of
				https://github.com/YosysHQ/yosys
				synced 2025-11-04 13:29:12 +00:00 
			
		
		
		
	Make SigSpec::is_fully_def use chunk iterator
This commit is contained in:
		
							parent
							
								
									8a88acd9b8
								
							
						
					
					
						commit
						b2de56cae2
					
				
					 1 changed files with 4 additions and 5 deletions
				
			
		| 
						 | 
				
			
			@ -5470,12 +5470,11 @@ bool RTLIL::SigSpec::is_fully_def() const
 | 
			
		|||
{
 | 
			
		||||
	cover("kernel.rtlil.sigspec.is_fully_def");
 | 
			
		||||
 | 
			
		||||
	pack();
 | 
			
		||||
	for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
 | 
			
		||||
		if (it->width > 0 && it->wire != NULL)
 | 
			
		||||
	for (auto &chunk : chunks()) {
 | 
			
		||||
		if (chunk.width > 0 && chunk.wire != NULL)
 | 
			
		||||
			return false;
 | 
			
		||||
		for (size_t i = 0; i < it->data.size(); i++)
 | 
			
		||||
			if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
 | 
			
		||||
		for (RTLIL::State d : chunk.data)
 | 
			
		||||
			if (d != RTLIL::State::S0 && d != RTLIL::State::S1)
 | 
			
		||||
				return false;
 | 
			
		||||
	}
 | 
			
		||||
	return true;
 | 
			
		||||
| 
						 | 
				
			
			
 | 
			
		|||
		Loading…
	
	Add table
		Add a link
		
	
		Reference in a new issue