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Error out on latches.

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This commit is contained in:
nella 2026-06-17 17:36:32 +02:00
parent 1023361d6c
commit b2d688dbf9
14 changed files with 149 additions and 37 deletions
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6
tests/arch/quicklogic/pp3/latches.ys
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@ -4,7 +4,7 @@ design -save read
hierarchy -top latchp
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_quicklogic
synth_quicklogic -latches auto
cd latchp # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT3
select -assert-count 3 t:inpad
@ -17,7 +17,7 @@ design -load read
hierarchy -top latchn
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_quicklogic
synth_quicklogic -latches auto
cd latchn # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT3
select -assert-count 3 t:inpad
@ -30,7 +30,7 @@ design -load read
hierarchy -top latchsr
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_quicklogic
synth_quicklogic -latches auto
cd latchsr # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT2
select -assert-count 1 t:LUT4