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nataliakokoromyti 2026-06-19 05:12:23 +00:00 • committed by GitHub
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tests/various/equiv_nocells.ys Normal file
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read_verilog <<EOT
module gold(input a, input b, output y);
assign y = a & b;
endmodule
module gate(input a, input b, output y);
assign y = a & b;
endmodule
EOT
equiv_make -nocells gold gate equiv
equiv_simple equiv
equiv_status -assert equiv