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removed comma

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williamzhu17 2025-05-08 17:39:16 -07:00
parent 8d20ed0637
commit b265ea9dcf
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tests/silimate/opt_balance_tree.ys
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@ -127,7 +127,7 @@ module top (
input wire b,
input wire c,
input wire d,
output wire [3:0] x,
output wire [3:0] x
);
assign x[0] = a & b;
assign x[1] = x[0] & c;