mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 05:19:11 +00:00
Code Activity

memory_bram hotfix for memories with width 1

Browse source
This commit is contained in:
Clifford Wolf 2015-01-06 23:59:53 +01:00
parent 08c13f635c
commit b26590f8ab
1 changed files with 3 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

6
passes/memory/memory_bram.cc
View file

@ -294,10 +294,10 @@ bool replace_cell(Cell *cell, const rules_t::bram_t &bram, const rules_t::match_
SigSpec rd_data = cell->getPort("\\RD_DATA");
SigSpec rd_addr = cell->getPort("\\RD_ADDR");
if (match.shuffle_enable)
if (match.shuffle_enable && bram.dbits >= match.shuffle_enable*2)
{
int bucket_size = bram.dbits / match.shuffle_enable;
log(" Shuffle enable and data bit to accommodate enable buckets of size %d..\n", bucket_size);
log(" Shuffle bit order to accommodate enable buckets of size %d..\n", bucket_size);
// extract unshuffled data/enable bits
@ -363,7 +363,7 @@ bool replace_cell(Cell *cell, const rules_t::bram_t &bram, const rules_t::match_
}
}
log(" Results of enable shuffling:");
log(" Results of bit order shuffling:");
for (int v : shuffle_map)
log(" %d", v);
log("\n");