mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 05:19:11 +00:00
Code Activity

Improve SVA tests, add Makefile and scripts

Browse source
This commit is contained in:
Clifford Wolf 2017-07-27 11:42:05 +02:00
parent 90d8329f64
commit b24f737759
11 changed files with 110 additions and 9 deletions
Download patch file Download diff file Expand all files Collapse all files

6
tests/sva/basic05.vhd
View file

@ -10,9 +10,9 @@ entity demo is
end entity;
architecture rtl of demo is
signal read : std_logic;
signal write : std_logic;
signal ready : std_logic;
signal read : std_logic := '0';
signal write : std_logic := '0';
signal ready : std_logic := '0';
begin
process (clock) begin
if (rising_edge(clock)) then