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Improve SVA tests, add Makefile and scripts
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11 changed files with 110 additions and 9 deletions
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@ -10,9 +10,9 @@ entity top is
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end entity;
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architecture rtl of top is
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signal read : std_logic;
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signal write : std_logic;
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signal ready : std_logic;
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signal read : std_logic := '0';
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signal write : std_logic := '0';
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signal ready : std_logic := '0';
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begin
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process (clock) begin
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if (rising_edge(clock)) then
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