mirror of
https://github.com/YosysHQ/yosys
synced 2025-08-25 12:36:02 +00:00
Improve SVA tests, add Makefile and scripts
This commit is contained in:
parent
90d8329f64
commit
b24f737759
11 changed files with 110 additions and 9 deletions
|
@ -4,7 +4,9 @@ module top (input logic clk, input logic selA, selB, QA, QB, output logic Q);
|
|||
if (selB) Q <= QB;
|
||||
end
|
||||
|
||||
check_selA: assert property ( @(posedge clk) selA|=> Q == $past(QA) );
|
||||
check_selB: assert property ( @(posedge clk) selB|=> Q == $past(QB) );
|
||||
assume_not_11: assume property ( @(posedge clk) !(selA& selB) );
|
||||
check_selA: assert property ( @(posedge clk) selA |=> Q == $past(QA) );
|
||||
check_selB: assert property ( @(posedge clk) selB |=> Q == $past(QB) );
|
||||
`ifndef FAIL
|
||||
assume_not_11: assume property ( @(posedge clk) !(selA & selB) );
|
||||
`endif
|
||||
endmodule
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue