mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 03:32:29 +00:00
Merge branch 'master' of github.com:YosysHQ/yosys
This commit is contained in:
Clifford Wolf
commit
b236faffa1
11 changed files with 256 additions and 35 deletions
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@ -36,7 +36,7 @@ struct OptLutWorker
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dict<RTLIL::Cell*, pool<RTLIL::Cell*>> luts_dlogics;
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dict<RTLIL::Cell*, pool<int>> luts_dlogic_inputs;
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int combined_count = 0;
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int eliminated_count = 0, combined_count = 0;
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bool evaluate_lut(RTLIL::Cell *lut, dict<SigBit, bool> inputs)
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{
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@ -189,8 +189,16 @@ struct OptLutWorker
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log("\n");
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log("Eliminating LUTs.\n");
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for (auto lut : luts)
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pool<RTLIL::Cell*> worklist = luts;
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while (worklist.size())
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{
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if (limit == 0)
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{
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log("Limit reached.\n");
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break;
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}
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auto lut = worklist.pop();
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SigSpec lut_input = sigmap(lut->getPort("\\A"));
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pool<int> &lut_dlogic_inputs = luts_dlogic_inputs[lut];
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@ -256,13 +264,24 @@ struct OptLutWorker
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else
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{
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SigSpec lut_output = lut->getPort("\\Y");
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for (auto &port : index.query_ports(lut_output))
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{
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if (port.cell != lut && luts.count(port.cell))
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worklist.insert(port.cell);
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}
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module->connect(lut_output, value);
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sigmap.add(lut_output, value);
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module->remove(lut);
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luts.erase(lut);
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luts_arity.erase(lut);
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luts_dlogics.erase(lut);
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luts_dlogic_inputs.erase(lut);
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eliminated_count++;
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if (limit > 0)
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limit--;
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}
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}
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}
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@ -270,7 +289,7 @@ struct OptLutWorker
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log("\n");
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log("Combining LUTs.\n");
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pool<RTLIL::Cell*> worklist = luts;
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worklist = luts;
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while (worklist.size())
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{
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if (limit == 0)
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@ -568,16 +587,20 @@ struct OptLutPass : public Pass {
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}
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extra_args(args, argidx, design);
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int total_count = 0;
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int eliminated_count = 0, combined_count = 0;
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for (auto module : design->selected_modules())
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{
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OptLutWorker worker(dlogic, module, limit - total_count);
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total_count += worker.combined_count;
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OptLutWorker worker(dlogic, module, limit - eliminated_count - combined_count);
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eliminated_count += worker.eliminated_count;
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combined_count += worker.combined_count;
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}
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if (total_count)
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if (eliminated_count)
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design->scratchpad_set_bool("opt.did_something", true);
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if (combined_count)
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design->scratchpad_set_bool("opt.did_something", true);
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log("\n");
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log("Combined %d LUTs.\n", total_count);
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log("Eliminated %d LUTs.\n", eliminated_count);
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log("Combined %d LUTs.\n", combined_count);
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}
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} OptLutPass;
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@ -43,18 +43,37 @@ struct DffinitPass : public Pass {
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log(" initial value of 1 or 0. (multi-bit values are not supported in this\n");
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log(" mode.)\n");
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log("\n");
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log(" -strinit <string for high> <string for low> \n");
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log(" use string values in the command line to represent a single-bit\n");
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log(" initial value of 1 or 0. (multi-bit values are not supported in this\n");
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log(" mode.)\n");
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log("\n");
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log(" -noreinit\n");
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log(" fail if the FF cell has already a defined initial value set in other\n");
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log(" passes and the initial value of the net it drives is not equal to\n");
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log(" the already defined initial value.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing DFFINIT pass (set INIT param on FF cells).\n");
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dict<IdString, dict<IdString, IdString>> ff_types;
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bool highlow_mode = false;
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bool highlow_mode = false, noreinit = false;
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std::string high_string, low_string;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-highlow") {
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highlow_mode = true;
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high_string = "high";
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low_string = "low";
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continue;
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}
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if (args[argidx] == "-strinit" && argidx+2 < args.size()) {
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highlow_mode = true;
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high_string = args[++argidx];
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low_string = args[++argidx];
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continue;
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}
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if (args[argidx] == "-ff" && argidx+3 < args.size()) {
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@ -64,6 +83,10 @@ struct DffinitPass : public Pass {
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ff_types[cell_name][output_port] = init_param;
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continue;
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}
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if (args[argidx] == "-noreinit") {
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noreinit = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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@ -112,6 +135,10 @@ struct DffinitPass : public Pass {
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continue;
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while (GetSize(value.bits) <= i)
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value.bits.push_back(State::S0);
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if (noreinit && value.bits[i] != State::Sx && value.bits[i] != init_bits.at(sig[i]))
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log_error("Trying to assign a different init value for %s.%s.%s which technically "
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"have a conflicted init value.\n",
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log_id(module), log_id(cell), log_id(it.second));
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value.bits[i] = init_bits.at(sig[i]);
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cleanup_bits.insert(sig[i]);
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}
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@ -121,9 +148,9 @@ struct DffinitPass : public Pass {
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log_error("Multi-bit init value for %s.%s.%s is incompatible with -highlow mode.\n",
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log_id(module), log_id(cell), log_id(it.second));
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if (value[0] == State::S1)
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value = Const("high");
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value = Const(high_string);
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else
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value = Const("low");
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value = Const(low_string);
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}
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log("Setting %s.%s.%s (port=%s, net=%s) to %s.\n", log_id(module), log_id(cell), log_id(it.second),
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@ -1,19 +1,19 @@
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module \$_DFF_N_ (input D, C, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(1'b0)); endmodule
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module \$_DFF_P_ (input D, C, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(1'b1), .sr(1'b0)); endmodule
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module \$_DFF_N_ (input D, C, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(1'b0)); endmodule
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module \$_DFF_P_ (input D, C, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(1'b1), .sr(1'b0)); endmodule
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module \$_DFFE_NN_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(E), .sr(1'b0)); endmodule
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module \$_DFFE_NP_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(E), .sr(1'b0)); endmodule
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module \$_DFFE_PN_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(1'b0)); endmodule
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module \$_DFFE_PP_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(1'b0)); endmodule
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module \$_DFFE_NN_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(E), .sr(1'b0)); endmodule
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module \$_DFFE_NP_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(E), .sr(1'b0)); endmodule
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module \$_DFFE_PN_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(1'b0)); endmodule
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module \$_DFFE_PP_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(1'b0)); endmodule
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module \$_DFF_NN0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
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module \$_DFF_NN1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
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module \$_DFF_NP0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
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module \$_DFF_NP1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
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module \$_DFF_PN0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C) , .ce(1'b1), .sr(R)); endmodule
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module \$_DFF_PN1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(1'b1), .sr(R)); endmodule
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module \$_DFF_PP0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(1'b1), .sr(R)); endmodule
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module \$_DFF_PP1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"), .SRMUX("SR"), . SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(1'b1), .sr(R)); endmodule
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module \$_DFF_NN0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
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module \$_DFF_NN1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
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module \$_DFF_NP0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
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module \$_DFF_NP1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
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module \$_DFF_PN0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C) , .ce(1'b1), .sr(R)); endmodule
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module \$_DFF_PN1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(1'b1), .sr(R)); endmodule
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module \$_DFF_PP0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(1'b1), .sr(R)); endmodule
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module \$_DFF_PP1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("SR"), . SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(1'b1), .sr(R)); endmodule
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module \$_DLATCH_N_ (E, D, Q);
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wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
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@ -170,6 +170,7 @@ struct SynthAnlogicPass : public ScriptPass
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{
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run("dffsr2dff");
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run("techmap -D NO_LUT -map +/anlogic/cells_map.v");
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run("dffinit -strinit SET RESET -ff AL_MAP_SEQ q REGSET -noreinit");
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run("opt_expr -mux_undef");
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run("simplemap");
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}
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@ -26,5 +26,5 @@ $(eval $(call add_share_file,share,techlibs/common/pmux2mux.v))
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$(eval $(call add_share_file,share,techlibs/common/adff2dff.v))
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$(eval $(call add_share_file,share,techlibs/common/dff2ff.v))
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$(eval $(call add_share_file,share,techlibs/common/gate2lut.v))
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$(eval $(call add_share_file,share,techlibs/common/cmp2lut.v))
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$(eval $(call add_share_file,share,techlibs/common/cells.lib))
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105
techlibs/common/cmp2lut.v
Normal file
105
techlibs/common/cmp2lut.v
Normal file
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@ -0,0 +1,105 @@
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// Certain arithmetic operations between a signal of width n and a constant can be directly mapped
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// to a single k-LUT (where n <= k). This is preferable to normal alumacc techmapping process
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// because for many targets, arithmetic techmapping creates hard logic (such as carry cells) which often
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// cannot be optimized further.
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//
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// TODO: Currently, only comparisons with 1-bit output are mapped. Potentially, all arithmetic cells
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// with n <= k inputs should be techmapped in this way, because this shortens the critical path
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// from n to 1 by avoiding carry chains.
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(* techmap_celltype = "$eq $ne $lt $le $gt $ge" *)
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module _90_lut_cmp_ (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 0;
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parameter B_WIDTH = 0;
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parameter Y_WIDTH = 0;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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parameter _TECHMAP_CELLTYPE_ = "";
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parameter _TECHMAP_CONSTMSK_A_ = 0;
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parameter _TECHMAP_CONSTVAL_A_ = 0;
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parameter _TECHMAP_CONSTMSK_B_ = 0;
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parameter _TECHMAP_CONSTVAL_B_ = 0;
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function automatic integer gen_lut;
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input integer width;
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input integer operation;
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input integer swap;
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input integer sign;
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input integer operand;
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integer n, i_var, i_cst, lhs, rhs, o_bit;
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begin
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gen_lut = width'b0;
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for (n = 0; n < (1 << width); n++) begin
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if (sign)
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i_var = n[width-1:0];
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else
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i_var = n;
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i_cst = operand;
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if (swap) begin
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lhs = i_cst;
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rhs = i_var;
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end else begin
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lhs = i_var;
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rhs = i_cst;
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end
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if (operation == 0)
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o_bit = (lhs < rhs);
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if (operation == 1)
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o_bit = (lhs <= rhs);
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if (operation == 2)
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o_bit = (lhs > rhs);
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if (operation == 3)
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o_bit = (lhs >= rhs);
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if (operation == 4)
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o_bit = (lhs == rhs);
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if (operation == 5)
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o_bit = (lhs != rhs);
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gen_lut = gen_lut | (o_bit << n);
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end
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end
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endfunction
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generate
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if (_TECHMAP_CELLTYPE_ == "$lt")
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localparam operation = 0;
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if (_TECHMAP_CELLTYPE_ == "$le")
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localparam operation = 1;
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if (_TECHMAP_CELLTYPE_ == "$gt")
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localparam operation = 2;
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if (_TECHMAP_CELLTYPE_ == "$ge")
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localparam operation = 3;
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if (_TECHMAP_CELLTYPE_ == "$eq")
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localparam operation = 4;
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if (_TECHMAP_CELLTYPE_ == "$ne")
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localparam operation = 5;
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if (A_WIDTH > `LUT_WIDTH || B_WIDTH > `LUT_WIDTH || Y_WIDTH != 1)
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wire _TECHMAP_FAIL_ = 1;
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else if (&_TECHMAP_CONSTMSK_B_)
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\$lut #(
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||||
.WIDTH(A_WIDTH),
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.LUT({ gen_lut(A_WIDTH, operation, 0, A_SIGNED && B_SIGNED, _TECHMAP_CONSTVAL_B_) })
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||||
) _TECHMAP_REPLACE_ (
|
||||
.A(A),
|
||||
.Y(Y)
|
||||
);
|
||||
else if (&_TECHMAP_CONSTMSK_A_)
|
||||
\$lut #(
|
||||
.WIDTH(B_WIDTH),
|
||||
.LUT({ gen_lut(B_WIDTH, operation, 1, A_SIGNED && B_SIGNED, _TECHMAP_CONSTVAL_A_) })
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.A(B),
|
||||
.Y(Y)
|
||||
);
|
||||
else
|
||||
wire _TECHMAP_FAIL_ = 1;
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
|
@ -51,6 +51,9 @@ struct SynthPass : public ScriptPass
|
|||
log(" -encfile <file>\n");
|
||||
log(" passed to 'fsm_recode' via 'fsm'\n");
|
||||
log("\n");
|
||||
log(" -lut <k>\n");
|
||||
log(" perform synthesis for a k-LUT architecture.\n");
|
||||
log("\n");
|
||||
log(" -nofsm\n");
|
||||
log(" do not run FSM optimization\n");
|
||||
log("\n");
|
||||
|
|
@ -80,6 +83,7 @@ struct SynthPass : public ScriptPass
|
|||
|
||||
string top_module, fsm_opts, memory_opts;
|
||||
bool autotop, flatten, noalumacc, nofsm, noabc, noshare;
|
||||
int lut;
|
||||
|
||||
void clear_flags() YS_OVERRIDE
|
||||
{
|
||||
|
|
@ -89,6 +93,7 @@ struct SynthPass : public ScriptPass
|
|||
|
||||
autotop = false;
|
||||
flatten = false;
|
||||
lut = 0;
|
||||
noalumacc = false;
|
||||
nofsm = false;
|
||||
noabc = false;
|
||||
|
|
@ -130,6 +135,10 @@ struct SynthPass : public ScriptPass
|
|||
flatten = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-lut") {
|
||||
lut = atoi(args[++argidx].c_str());
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-nofsm") {
|
||||
nofsm = true;
|
||||
continue;
|
||||
|
|
@ -186,19 +195,23 @@ struct SynthPass : public ScriptPass
|
|||
{
|
||||
run("proc");
|
||||
if (help_mode || flatten)
|
||||
run("flatten", "(if -flatten)");
|
||||
run("flatten", " (if -flatten)");
|
||||
run("opt_expr");
|
||||
run("opt_clean");
|
||||
run("check");
|
||||
run("opt");
|
||||
run("wreduce");
|
||||
if (help_mode)
|
||||
run("techmap -map +/cmp2lut.v", " (if -lut)");
|
||||
else
|
||||
run(stringf("techmap -map +/cmp2lut.v -D LUT_WIDTH=%d", lut));
|
||||
if (!noalumacc)
|
||||
run("alumacc");
|
||||
run("alumacc", " (unless -noalumacc)");
|
||||
if (!noshare)
|
||||
run("share");
|
||||
run("share", " (unless -noshare)");
|
||||
run("opt");
|
||||
if (!nofsm)
|
||||
run("fsm" + fsm_opts);
|
||||
run("fsm" + fsm_opts, " (unless -nofsm)");
|
||||
run("opt -fast");
|
||||
run("memory -nomap" + memory_opts);
|
||||
run("opt_clean");
|
||||
|
|
@ -210,12 +223,33 @@ struct SynthPass : public ScriptPass
|
|||
run("memory_map");
|
||||
run("opt -full");
|
||||
run("techmap");
|
||||
if (help_mode)
|
||||
{
|
||||
run("techmap -map +/gate2lut.v", "(if -noabc and -lut)");
|
||||
run("clean; opt_lut", " (if -noabc and -lut)");
|
||||
}
|
||||
else if (noabc && lut)
|
||||
{
|
||||
run(stringf("techmap -map +/gate2lut.v -D LUT_WIDTH=%d", lut));
|
||||
run("clean; opt_lut");
|
||||
}
|
||||
run("opt -fast");
|
||||
|
||||
if (!noabc) {
|
||||
#ifdef YOSYS_ENABLE_ABC
|
||||
run("abc -fast");
|
||||
run("opt -fast");
|
||||
if (help_mode)
|
||||
{
|
||||
run("abc -fast", " (unless -noabc, unless -lut)");
|
||||
run("abc -fast -lut k", "(unless -noabc, if -lut)");
|
||||
}
|
||||
else
|
||||
{
|
||||
if (lut)
|
||||
run(stringf("abc -fast -lut %d", lut));
|
||||
else
|
||||
run("abc -fast");
|
||||
}
|
||||
run("opt -fast", " (unless -noabc)");
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -226,7 +226,7 @@ struct SynthIce40Pass : public ScriptPass
|
|||
|
||||
if (check_label("coarse"))
|
||||
{
|
||||
run("synth -run coarse");
|
||||
run("synth -lut 4 -run coarse");
|
||||
}
|
||||
|
||||
if (!nobram && check_label("bram", "(skip if -nobram)"))
|
||||
|
|
|
|||
|
|
@ -1,4 +1,6 @@
|
|||
simplemap
|
||||
equiv_opt -assert techmap -map +/gate2lut.v -D LUT_WIDTH=4
|
||||
equiv_opt -assert techmap -D LUT_WIDTH=4 -map +/cmp2lut.v
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$lut
|
||||
equiv_opt -assert techmap -D LUT_WIDTH=4 -map +/gate2lut.v
|
||||
design -load postopt
|
||||
select -assert-count 0 t:* t:$lut %d
|
||||
|
|
|
|||
29
tests/lut/map_cmp.v
Normal file
29
tests/lut/map_cmp.v
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
module top(...);
|
||||
input [3:0] a;
|
||||
|
||||
output o1_1 = 4'b1010 <= a;
|
||||
output o1_2 = 4'b1010 < a;
|
||||
output o1_3 = 4'b1010 >= a;
|
||||
output o1_4 = 4'b1010 > a;
|
||||
output o1_5 = 4'b1010 == a;
|
||||
output o1_6 = 4'b1010 != a;
|
||||
|
||||
output o2_1 = a <= 4'b1010;
|
||||
output o2_2 = a < 4'b1010;
|
||||
output o2_3 = a >= 4'b1010;
|
||||
output o2_4 = a > 4'b1010;
|
||||
output o2_5 = a == 4'b1010;
|
||||
output o2_6 = a != 4'b1010;
|
||||
|
||||
output o3_1 = 4'sb0101 <= $signed(a);
|
||||
output o3_2 = 4'sb0101 < $signed(a);
|
||||
output o3_3 = 4'sb0101 >= $signed(a);
|
||||
output o3_4 = 4'sb0101 > $signed(a);
|
||||
output o3_5 = 4'sb0101 == $signed(a);
|
||||
output o3_6 = 4'sb0101 != $signed(a);
|
||||
|
||||
output o4_1 = $signed(a) <= 4'sb0000;
|
||||
output o4_2 = $signed(a) < 4'sb0000;
|
||||
output o4_3 = $signed(a) >= 4'sb0000;
|
||||
output o4_4 = $signed(a) > 4'sb0000;
|
||||
endmodule
|
||||
0
tests/lut/run-test.sh
Normal file → Executable file
0
tests/lut/run-test.sh
Normal file → Executable file
Loading…
Add table
Add a link
Reference in a new issue