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This commit is contained in:
Miodrag Milanovic 2024-03-13 10:57:58 +01:00
parent 71f0984dc9
commit b202126c76
7 changed files with 2118 additions and 1833 deletions
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602
techlibs/nanoxplore/cells_wrap_u.v
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@ -2704,3 +2704,605 @@ module UMUL48x36_4DSP(clk, rst, A, B, Z);
input rst;
parameter piped = "true";
endmodule
//TODO
module NX_HSSL_U_FULL(hssl_clk_user_tx_i, hssl_clk_user_rx_i, hssl_clk_ref_i, hssl_clock_o, hssl_rclock_o, usr_dyn_cfg_en_i, usr_dyn_cfg_calibration_cs_n_i, usr_dyn_cfg_we_n_i, usr_dyn_cfg_wdata_sel_i, usr_pll_pma_rst_n_i, usr_pll_pma_pwr_down_n_i, usr_main_rst_n_i, usr_pll_lock_o, usr_pll_pma_lock_analog_o, usr_pll_ckfb_lock_o, usr_calibrate_pma_out_o, usr_main_async_debug_ack_i, usr_main_async_debug_req_o, scan_en_i, usr_tx0_ctrl_replace_en_i, usr_tx0_rst_n_i
, usr_tx0_busy_o, usr_tx0_ctrl_invalid_k_o, usr_tx0_ctrl_driver_pwrdwn_n_i, usr_tx0_pma_clk_en_i, usr_tx0_pma_tx_clk_o, usr_rx0_ctrl_dscr_en_i, usr_rx0_ctrl_dec_en_i, usr_rx0_ctrl_align_en_i, usr_rx0_ctrl_align_sync_i, usr_rx0_ctrl_replace_en_i, usr_rx0_ctrl_el_buff_rst_i, usr_rx0_rst_n_i, usr_rx0_pma_rst_n_i, usr_rx0_pma_m_eye_rst_i, usr_rx0_pma_pwr_down_n_i, usr_rx0_ctrl_char_is_aligned_o, usr_rx0_ctrl_valid_realign_o, usr_rx0_busy_o, usr_rx0_pma_loss_of_signal_o, usr_rx0_pma_ll_fast_locked_o, usr_rx0_pma_ll_slow_locked_o
, usr_rx0_pma_pll_lock_o, usr_rx0_pma_pll_lock_track_o, usr_tx1_ctrl_replace_en_i, usr_tx1_rst_n_i, usr_tx1_busy_o, usr_tx1_ctrl_invalid_k_o, usr_tx1_ctrl_driver_pwrdwn_n_i, usr_tx1_pma_clk_en_i, usr_tx1_pma_tx_clk_o, usr_rx1_ctrl_dscr_en_i, usr_rx1_ctrl_dec_en_i, usr_rx1_ctrl_align_en_i, usr_rx1_ctrl_align_sync_i, usr_rx1_ctrl_replace_en_i, usr_rx1_ctrl_el_buff_rst_i, usr_rx1_rst_n_i, usr_rx1_pma_rst_n_i, usr_rx1_pma_m_eye_rst_i, usr_rx1_pma_pwr_down_n_i, usr_rx1_ctrl_char_is_aligned_o, usr_rx1_ctrl_valid_realign_o
, usr_rx1_busy_o, usr_rx1_pma_loss_of_signal_o, usr_rx1_pma_ll_fast_locked_o, usr_rx1_pma_ll_slow_locked_o, usr_rx1_pma_pll_lock_o, usr_rx1_pma_pll_lock_track_o, usr_tx2_ctrl_replace_en_i, usr_tx2_rst_n_i, usr_tx2_busy_o, usr_tx2_ctrl_invalid_k_o, usr_tx2_ctrl_driver_pwrdwn_n_i, usr_tx2_pma_clk_en_i, usr_tx2_pma_tx_clk_o, usr_rx2_ctrl_dscr_en_i, usr_rx2_ctrl_dec_en_i, usr_rx2_ctrl_align_en_i, usr_rx2_ctrl_align_sync_i, usr_rx2_ctrl_replace_en_i, usr_rx2_ctrl_el_buff_rst_i, usr_rx2_rst_n_i, usr_rx2_pma_rst_n_i
, usr_rx2_pma_m_eye_rst_i, usr_rx2_pma_pwr_down_n_i, usr_rx2_ctrl_char_is_aligned_o, usr_rx2_ctrl_valid_realign_o, usr_rx2_busy_o, usr_rx2_pma_loss_of_signal_o, usr_rx2_pma_ll_fast_locked_o, usr_rx2_pma_ll_slow_locked_o, usr_rx2_pma_pll_lock_o, usr_rx2_pma_pll_lock_track_o, usr_tx3_ctrl_replace_en_i, usr_tx3_rst_n_i, usr_tx3_busy_o, usr_tx3_ctrl_invalid_k_o, usr_tx3_ctrl_driver_pwrdwn_n_i, usr_tx3_pma_clk_en_i, usr_tx3_pma_tx_clk_o, usr_rx3_ctrl_dscr_en_i, usr_rx3_ctrl_dec_en_i, usr_rx3_ctrl_align_en_i, usr_rx3_ctrl_align_sync_i
, usr_rx3_ctrl_replace_en_i, usr_rx3_ctrl_el_buff_rst_i, usr_rx3_rst_n_i, usr_rx3_pma_rst_n_i, usr_rx3_pma_m_eye_rst_i, usr_rx3_pma_pwr_down_n_i, usr_rx3_ctrl_char_is_aligned_o, usr_rx3_ctrl_valid_realign_o, usr_rx3_busy_o, usr_rx3_pma_loss_of_signal_o, usr_rx3_pma_ll_fast_locked_o, usr_rx3_pma_ll_slow_locked_o, usr_rx3_pma_pll_lock_o, usr_rx3_pma_pll_lock_track_o, usr_tx0_ctrl_enc_en_i, usr_tx0_ctrl_char_is_k_i, usr_tx0_ctrl_scr_en_i, usr_tx0_ctrl_end_of_multiframe_i, usr_tx0_ctrl_end_of_frame_i, usr_tx0_data_i, usr_rx0_data_o
, usr_rx0_ctrl_ovs_bit_sel_i, usr_rx0_ctrl_char_is_comma_o, usr_rx0_ctrl_char_is_k_o, usr_rx0_ctrl_not_in_table_o, usr_rx0_ctrl_disp_err_o, usr_rx0_ctrl_char_is_a_o, usr_rx0_ctrl_char_is_f_o, usr_rx0_test_o, usr_tx1_ctrl_enc_en_i, usr_tx1_ctrl_char_is_k_i, usr_tx1_ctrl_scr_en_i, usr_tx1_ctrl_end_of_multiframe_i, usr_tx1_ctrl_end_of_frame_i, usr_tx1_data_i, usr_rx1_data_o, usr_rx1_ctrl_ovs_bit_sel_i, usr_rx1_ctrl_char_is_comma_o, usr_rx1_ctrl_char_is_k_o, usr_rx1_ctrl_not_in_table_o, usr_rx1_ctrl_disp_err_o, usr_rx1_ctrl_char_is_a_o
, usr_rx1_ctrl_char_is_f_o, usr_rx1_test_o, usr_tx2_ctrl_enc_en_i, usr_tx2_ctrl_char_is_k_i, usr_tx2_ctrl_scr_en_i, usr_tx2_ctrl_end_of_multiframe_i, usr_tx2_ctrl_end_of_frame_i, usr_tx2_data_i, usr_rx2_data_o, usr_rx2_ctrl_ovs_bit_sel_i, usr_rx2_ctrl_char_is_comma_o, usr_rx2_ctrl_char_is_k_o, usr_rx2_ctrl_not_in_table_o, usr_rx2_ctrl_disp_err_o, usr_rx2_ctrl_char_is_a_o, usr_rx2_ctrl_char_is_f_o, usr_rx2_test_o, usr_tx3_ctrl_enc_en_i, usr_tx3_ctrl_char_is_k_i, usr_tx3_ctrl_scr_en_i, usr_tx3_ctrl_end_of_multiframe_i
, usr_tx3_ctrl_end_of_frame_i, usr_tx3_data_i, usr_rx3_data_o, usr_rx3_ctrl_ovs_bit_sel_i, usr_rx3_ctrl_char_is_comma_o, usr_rx3_ctrl_char_is_k_o, usr_rx3_ctrl_not_in_table_o, usr_rx3_ctrl_disp_err_o, usr_rx3_ctrl_char_is_a_o, usr_rx3_ctrl_char_is_f_o, usr_rx3_test_o, usr_dyn_cfg_addr_i, usr_dyn_cfg_wdata_i, usr_main_async_debug_lane_sel_i, usr_main_rx_pma_ll_out_o, scan_in_i, scan_out_o, usr_rx0_ctrl_debug_sel_i, usr_rx1_ctrl_debug_sel_i, usr_rx2_ctrl_debug_sel_i, usr_rx3_ctrl_debug_sel_i
, usr_dyn_cfg_lane_cs_n_i);
input hssl_clk_ref_i;
input hssl_clk_user_rx_i;
input hssl_clk_user_tx_i;
output hssl_clock_o;
output hssl_rclock_o;
input scan_en_i;
input [7:0] scan_in_i;
output [7:0] scan_out_o;
output usr_calibrate_pma_out_o;
input [3:0] usr_dyn_cfg_addr_i;
input usr_dyn_cfg_calibration_cs_n_i;
input usr_dyn_cfg_en_i;
input [3:0] usr_dyn_cfg_lane_cs_n_i;
input [11:0] usr_dyn_cfg_wdata_i;
input usr_dyn_cfg_wdata_sel_i;
input usr_dyn_cfg_we_n_i;
input usr_main_async_debug_ack_i;
input [1:0] usr_main_async_debug_lane_sel_i;
output usr_main_async_debug_req_o;
input usr_main_rst_n_i;
output [19:0] usr_main_rx_pma_ll_out_o;
output usr_pll_ckfb_lock_o;
output usr_pll_lock_o;
output usr_pll_pma_lock_analog_o;
input usr_pll_pma_pwr_down_n_i;
input usr_pll_pma_rst_n_i;
output usr_rx0_busy_o;
input usr_rx0_ctrl_align_en_i;
input usr_rx0_ctrl_align_sync_i;
output [7:0] usr_rx0_ctrl_char_is_a_o;
output usr_rx0_ctrl_char_is_aligned_o;
output [7:0] usr_rx0_ctrl_char_is_comma_o;
output [7:0] usr_rx0_ctrl_char_is_f_o;
output [7:0] usr_rx0_ctrl_char_is_k_o;
input [2:0] usr_rx0_ctrl_debug_sel_i;
input usr_rx0_ctrl_dec_en_i;
output [7:0] usr_rx0_ctrl_disp_err_o;
input usr_rx0_ctrl_dscr_en_i;
input usr_rx0_ctrl_el_buff_rst_i;
output [7:0] usr_rx0_ctrl_not_in_table_o;
input [1:0] usr_rx0_ctrl_ovs_bit_sel_i;
input usr_rx0_ctrl_replace_en_i;
output usr_rx0_ctrl_valid_realign_o;
output [63:0] usr_rx0_data_o;
output usr_rx0_pma_ll_fast_locked_o;
output usr_rx0_pma_ll_slow_locked_o;
output usr_rx0_pma_loss_of_signal_o;
input usr_rx0_pma_m_eye_rst_i;
output usr_rx0_pma_pll_lock_o;
output usr_rx0_pma_pll_lock_track_o;
input usr_rx0_pma_pwr_down_n_i;
input usr_rx0_pma_rst_n_i;
input usr_rx0_rst_n_i;
output [7:0] usr_rx0_test_o;
output usr_rx1_busy_o;
input usr_rx1_ctrl_align_en_i;
input usr_rx1_ctrl_align_sync_i;
output [7:0] usr_rx1_ctrl_char_is_a_o;
output usr_rx1_ctrl_char_is_aligned_o;
output [7:0] usr_rx1_ctrl_char_is_comma_o;
output [7:0] usr_rx1_ctrl_char_is_f_o;
output [7:0] usr_rx1_ctrl_char_is_k_o;
input [2:0] usr_rx1_ctrl_debug_sel_i;
input usr_rx1_ctrl_dec_en_i;
output [7:0] usr_rx1_ctrl_disp_err_o;
input usr_rx1_ctrl_dscr_en_i;
input usr_rx1_ctrl_el_buff_rst_i;
output [7:0] usr_rx1_ctrl_not_in_table_o;
input [1:0] usr_rx1_ctrl_ovs_bit_sel_i;
input usr_rx1_ctrl_replace_en_i;
output usr_rx1_ctrl_valid_realign_o;
output [63:0] usr_rx1_data_o;
output usr_rx1_pma_ll_fast_locked_o;
output usr_rx1_pma_ll_slow_locked_o;
output usr_rx1_pma_loss_of_signal_o;
input usr_rx1_pma_m_eye_rst_i;
output usr_rx1_pma_pll_lock_o;
output usr_rx1_pma_pll_lock_track_o;
input usr_rx1_pma_pwr_down_n_i;
input usr_rx1_pma_rst_n_i;
input usr_rx1_rst_n_i;
output [7:0] usr_rx1_test_o;
output usr_rx2_busy_o;
input usr_rx2_ctrl_align_en_i;
input usr_rx2_ctrl_align_sync_i;
output [7:0] usr_rx2_ctrl_char_is_a_o;
output usr_rx2_ctrl_char_is_aligned_o;
output [7:0] usr_rx2_ctrl_char_is_comma_o;
output [7:0] usr_rx2_ctrl_char_is_f_o;
output [7:0] usr_rx2_ctrl_char_is_k_o;
input [2:0] usr_rx2_ctrl_debug_sel_i;
input usr_rx2_ctrl_dec_en_i;
output [7:0] usr_rx2_ctrl_disp_err_o;
input usr_rx2_ctrl_dscr_en_i;
input usr_rx2_ctrl_el_buff_rst_i;
output [7:0] usr_rx2_ctrl_not_in_table_o;
input [1:0] usr_rx2_ctrl_ovs_bit_sel_i;
input usr_rx2_ctrl_replace_en_i;
output usr_rx2_ctrl_valid_realign_o;
output [63:0] usr_rx2_data_o;
output usr_rx2_pma_ll_fast_locked_o;
output usr_rx2_pma_ll_slow_locked_o;
output usr_rx2_pma_loss_of_signal_o;
input usr_rx2_pma_m_eye_rst_i;
output usr_rx2_pma_pll_lock_o;
output usr_rx2_pma_pll_lock_track_o;
input usr_rx2_pma_pwr_down_n_i;
input usr_rx2_pma_rst_n_i;
input usr_rx2_rst_n_i;
output [7:0] usr_rx2_test_o;
output usr_rx3_busy_o;
input usr_rx3_ctrl_align_en_i;
input usr_rx3_ctrl_align_sync_i;
output [7:0] usr_rx3_ctrl_char_is_a_o;
output usr_rx3_ctrl_char_is_aligned_o;
output [7:0] usr_rx3_ctrl_char_is_comma_o;
output [7:0] usr_rx3_ctrl_char_is_f_o;
output [7:0] usr_rx3_ctrl_char_is_k_o;
input [2:0] usr_rx3_ctrl_debug_sel_i;
input usr_rx3_ctrl_dec_en_i;
output [7:0] usr_rx3_ctrl_disp_err_o;
input usr_rx3_ctrl_dscr_en_i;
input usr_rx3_ctrl_el_buff_rst_i;
output [7:0] usr_rx3_ctrl_not_in_table_o;
input [1:0] usr_rx3_ctrl_ovs_bit_sel_i;
input usr_rx3_ctrl_replace_en_i;
output usr_rx3_ctrl_valid_realign_o;
output [63:0] usr_rx3_data_o;
output usr_rx3_pma_ll_fast_locked_o;
output usr_rx3_pma_ll_slow_locked_o;
output usr_rx3_pma_loss_of_signal_o;
input usr_rx3_pma_m_eye_rst_i;
output usr_rx3_pma_pll_lock_o;
output usr_rx3_pma_pll_lock_track_o;
input usr_rx3_pma_pwr_down_n_i;
input usr_rx3_pma_rst_n_i;
input usr_rx3_rst_n_i;
output [7:0] usr_rx3_test_o;
output usr_tx0_busy_o;
input [7:0] usr_tx0_ctrl_char_is_k_i;
input usr_tx0_ctrl_driver_pwrdwn_n_i;
input [7:0] usr_tx0_ctrl_enc_en_i;
input [7:0] usr_tx0_ctrl_end_of_frame_i;
input [7:0] usr_tx0_ctrl_end_of_multiframe_i;
output usr_tx0_ctrl_invalid_k_o;
input usr_tx0_ctrl_replace_en_i;
input [7:0] usr_tx0_ctrl_scr_en_i;
input [63:0] usr_tx0_data_i;
input usr_tx0_pma_clk_en_i;
output usr_tx0_pma_tx_clk_o;
input usr_tx0_rst_n_i;
output usr_tx1_busy_o;
input [7:0] usr_tx1_ctrl_char_is_k_i;
input usr_tx1_ctrl_driver_pwrdwn_n_i;
input [7:0] usr_tx1_ctrl_enc_en_i;
input [7:0] usr_tx1_ctrl_end_of_frame_i;
input [7:0] usr_tx1_ctrl_end_of_multiframe_i;
output usr_tx1_ctrl_invalid_k_o;
input usr_tx1_ctrl_replace_en_i;
input [7:0] usr_tx1_ctrl_scr_en_i;
input [63:0] usr_tx1_data_i;
input usr_tx1_pma_clk_en_i;
output usr_tx1_pma_tx_clk_o;
input usr_tx1_rst_n_i;
output usr_tx2_busy_o;
input [7:0] usr_tx2_ctrl_char_is_k_i;
input usr_tx2_ctrl_driver_pwrdwn_n_i;
input [7:0] usr_tx2_ctrl_enc_en_i;
input [7:0] usr_tx2_ctrl_end_of_frame_i;
input [7:0] usr_tx2_ctrl_end_of_multiframe_i;
output usr_tx2_ctrl_invalid_k_o;
input usr_tx2_ctrl_replace_en_i;
input [7:0] usr_tx2_ctrl_scr_en_i;
input [63:0] usr_tx2_data_i;
input usr_tx2_pma_clk_en_i;
output usr_tx2_pma_tx_clk_o;
input usr_tx2_rst_n_i;
output usr_tx3_busy_o;
input [7:0] usr_tx3_ctrl_char_is_k_i;
input usr_tx3_ctrl_driver_pwrdwn_n_i;
input [7:0] usr_tx3_ctrl_enc_en_i;
input [7:0] usr_tx3_ctrl_end_of_frame_i;
input [7:0] usr_tx3_ctrl_end_of_multiframe_i;
output usr_tx3_ctrl_invalid_k_o;
input usr_tx3_ctrl_replace_en_i;
input [7:0] usr_tx3_ctrl_scr_en_i;
input [63:0] usr_tx3_data_i;
input usr_tx3_pma_clk_en_i;
output usr_tx3_pma_tx_clk_o;
input usr_tx3_rst_n_i;
parameter cfg_dyn_all_rx_pma_m_eye_coarse_ena_i = 1'b0;
parameter cfg_dyn_all_rx_pma_m_eye_dn_i = 1'b0;
parameter cfg_dyn_all_rx_pma_m_eye_fine_ena_i = 1'b0;
parameter cfg_dyn_all_rx_pma_m_eye_i = 1'b0;
parameter cfg_dyn_all_rx_pma_m_eye_step_i = 4'b0000;
parameter cfg_dyn_all_rx_pma_m_eye_up_i = 1'b0;
parameter cfg_dyn_all_rx_pma_threshold_1 = 5'b00000;
parameter cfg_dyn_all_rx_pma_threshold_2 = 5'b00000;
parameter cfg_dyn_all_rx_pma_trim_locked_i = 3'b000;
parameter cfg_dyn_all_rx_pma_trim_mode_i = 2'b00;
parameter cfg_dyn_all_rx_pma_trim_unlocked_i = 3'b000;
parameter cfg_dyn_rx0_pma_ctle_cap_p_i = 4'b0000;
parameter cfg_dyn_rx0_pma_ctle_res_p_i = 4'b0000;
parameter cfg_dyn_rx0_pma_dfe_idac_tap1_n_i = 6'b000000;
parameter cfg_dyn_rx0_pma_dfe_idac_tap2_n_i = 6'b000000;
parameter cfg_dyn_rx0_pma_dfe_idac_tap3_n_i = 6'b000000;
parameter cfg_dyn_rx0_pma_dfe_idac_tap4_n_i = 6'b000000;
parameter cfg_dyn_rx0_pma_termination_cmd_i = 6'b000000;
parameter cfg_dyn_rx1_pma_ctle_cap_p_i = 4'b0000;
parameter cfg_dyn_rx1_pma_ctle_res_p_i = 4'b0000;
parameter cfg_dyn_rx1_pma_dfe_idac_tap1_n_i = 6'b000000;
parameter cfg_dyn_rx1_pma_dfe_idac_tap2_n_i = 6'b000000;
parameter cfg_dyn_rx1_pma_dfe_idac_tap3_n_i = 6'b000000;
parameter cfg_dyn_rx1_pma_dfe_idac_tap4_n_i = 6'b000000;
parameter cfg_dyn_rx1_pma_termination_cmd_i = 6'b000000;
parameter cfg_dyn_rx2_pma_ctle_cap_p_i = 4'b0000;
parameter cfg_dyn_rx2_pma_ctle_res_p_i = 4'b0000;
parameter cfg_dyn_rx2_pma_dfe_idac_tap1_n_i = 6'b000000;
parameter cfg_dyn_rx2_pma_dfe_idac_tap2_n_i = 6'b000000;
parameter cfg_dyn_rx2_pma_dfe_idac_tap3_n_i = 6'b000000;
parameter cfg_dyn_rx2_pma_dfe_idac_tap4_n_i = 6'b000000;
parameter cfg_dyn_rx2_pma_termination_cmd_i = 6'b000000;
parameter cfg_dyn_rx3_pma_ctle_cap_p_i = 4'b0000;
parameter cfg_dyn_rx3_pma_ctle_res_p_i = 4'b0000;
parameter cfg_dyn_rx3_pma_dfe_idac_tap1_n_i = 6'b000000;
parameter cfg_dyn_rx3_pma_dfe_idac_tap2_n_i = 6'b000000;
parameter cfg_dyn_rx3_pma_dfe_idac_tap3_n_i = 6'b000000;
parameter cfg_dyn_rx3_pma_dfe_idac_tap4_n_i = 6'b000000;
parameter cfg_dyn_rx3_pma_termination_cmd_i = 6'b000000;
parameter cfg_dyn_tx0_pma_main_en_i = 6'b000000;
parameter cfg_dyn_tx0_pma_main_sign_i = 1'b0;
parameter cfg_dyn_tx0_pma_margin_input_i = 9'b000000000;
parameter cfg_dyn_tx0_pma_margin_sel_i = 9'b000000000;
parameter cfg_dyn_tx0_pma_post_en_i = 5'b00000;
parameter cfg_dyn_tx0_pma_post_sel_i = 8'b00000000;
parameter cfg_dyn_tx0_pma_post_sign_i = 1'b0;
parameter cfg_dyn_tx0_pma_pre_en_i = 1'b0;
parameter cfg_dyn_tx0_pma_pre_sel_i = 4'b0000;
parameter cfg_dyn_tx0_pma_pre_sign_i = 1'b0;
parameter cfg_dyn_tx1_pma_main_en_i = 6'b000000;
parameter cfg_dyn_tx1_pma_main_sign_i = 1'b0;
parameter cfg_dyn_tx1_pma_margin_input_i = 9'b000000000;
parameter cfg_dyn_tx1_pma_margin_sel_i = 9'b000000000;
parameter cfg_dyn_tx1_pma_post_en_i = 5'b00000;
parameter cfg_dyn_tx1_pma_post_sel_i = 8'b00000000;
parameter cfg_dyn_tx1_pma_post_sign_i = 1'b0;
parameter cfg_dyn_tx1_pma_pre_en_i = 1'b0;
parameter cfg_dyn_tx1_pma_pre_sel_i = 4'b0000;
parameter cfg_dyn_tx1_pma_pre_sign_i = 1'b0;
parameter cfg_dyn_tx2_pma_main_en_i = 6'b000000;
parameter cfg_dyn_tx2_pma_main_sign_i = 1'b0;
parameter cfg_dyn_tx2_pma_margin_input_i = 9'b000000000;
parameter cfg_dyn_tx2_pma_margin_sel_i = 9'b000000000;
parameter cfg_dyn_tx2_pma_post_en_i = 5'b00000;
parameter cfg_dyn_tx2_pma_post_sel_i = 8'b00000000;
parameter cfg_dyn_tx2_pma_post_sign_i = 1'b0;
parameter cfg_dyn_tx2_pma_pre_en_i = 1'b0;
parameter cfg_dyn_tx2_pma_pre_sel_i = 4'b0000;
parameter cfg_dyn_tx2_pma_pre_sign_i = 1'b0;
parameter cfg_dyn_tx3_pma_main_en_i = 6'b000000;
parameter cfg_dyn_tx3_pma_main_sign_i = 1'b0;
parameter cfg_dyn_tx3_pma_margin_input_i = 9'b000000000;
parameter cfg_dyn_tx3_pma_margin_sel_i = 9'b000000000;
parameter cfg_dyn_tx3_pma_post_en_i = 5'b00000;
parameter cfg_dyn_tx3_pma_post_sel_i = 8'b00000000;
parameter cfg_dyn_tx3_pma_post_sign_i = 1'b0;
parameter cfg_dyn_tx3_pma_pre_en_i = 1'b0;
parameter cfg_dyn_tx3_pma_pre_sel_i = 4'b0000;
parameter cfg_dyn_tx3_pma_pre_sign_i = 1'b0;
parameter cfg_main_clk_to_fabric_div_en_i = 1'b0;
parameter cfg_main_clk_to_fabric_div_mode_i = 1'b0;
parameter cfg_main_clk_to_fabric_sel_i = 1'b0;
parameter cfg_main_rclk_to_fabric_sel_i = 2'b00;
parameter cfg_main_use_only_usr_clock_i = 1'b0;
parameter cfg_pcs_ovs_en_i = 1'b0;
parameter cfg_pcs_ovs_mode_i = 1'b0;
parameter cfg_pcs_pll_lock_ppm_i = 3'b000;
parameter cfg_pcs_word_len_i = 2'b00;
parameter cfg_pll_pma_ckref_ext_i = 1'b0;
parameter cfg_pll_pma_cpump_i = 4'b0000;
parameter cfg_pll_pma_divl_i = 2'b00;
parameter cfg_pll_pma_divm_i = 1'b0;
parameter cfg_pll_pma_divn_i = 2'b00;
parameter cfg_pll_pma_gbx_en_i = 1'b0;
parameter cfg_pll_pma_int_data_len_i = 1'b0;
parameter cfg_pll_pma_lvds_en_i = 1'b0;
parameter cfg_pll_pma_lvds_mux_i = 1'b0;
parameter cfg_pll_pma_mux_ckref_i = 1'b0;
parameter cfg_rx0_gearbox_en_i = 1'b0;
parameter cfg_rx0_gearbox_mode_i = 1'b0;
parameter cfg_rx0_pcs_8b_dscr_sel_i = 1'b0;
parameter cfg_rx0_pcs_align_bypass_i = 1'b0;
parameter cfg_rx0_pcs_buffers_bypass_i = 1'b0;
parameter cfg_rx0_pcs_buffers_use_cdc_i = 1'b0;
parameter cfg_rx0_pcs_bypass_pma_cdc_i = 1'b0;
parameter cfg_rx0_pcs_bypass_usr_cdc_i = 1'b0;
parameter cfg_rx0_pcs_comma_mask_i = 10'b0000000000;
parameter cfg_rx0_pcs_debug_en_i = 1'b0;
parameter cfg_rx0_pcs_dec_bypass_i = 1'b0;
parameter cfg_rx0_pcs_dscr_bypass_i = 1'b0;
parameter cfg_rx0_pcs_el_buff_diff_bef_comp_i = 4'b0000;
parameter cfg_rx0_pcs_el_buff_max_comp_i = 4'b0000;
parameter cfg_rx0_pcs_el_buff_only_one_skp_i = 1'b0;
parameter cfg_rx0_pcs_el_buff_skp_char_0_i = 9'b000000000;
parameter cfg_rx0_pcs_el_buff_skp_char_1_i = 9'b000000000;
parameter cfg_rx0_pcs_el_buff_skp_char_2_i = 9'b000000000;
parameter cfg_rx0_pcs_el_buff_skp_char_3_i = 9'b000000000;
parameter cfg_rx0_pcs_el_buff_skp_header_0_i = 9'b000000000;
parameter cfg_rx0_pcs_el_buff_skp_header_1_i = 9'b000000000;
parameter cfg_rx0_pcs_el_buff_skp_header_2_i = 9'b000000000;
parameter cfg_rx0_pcs_el_buff_skp_header_3_i = 9'b000000000;
parameter cfg_rx0_pcs_el_buff_skp_header_size_i = 2'b00;
parameter cfg_rx0_pcs_el_buff_skp_seq_size_i = 2'b00;
parameter cfg_rx0_pcs_fsm_sel_i = 2'b00;
parameter cfg_rx0_pcs_fsm_watchdog_en_i = 1'b0;
parameter cfg_rx0_pcs_loopback_i = 1'b0;
parameter cfg_rx0_pcs_m_comma_en_i = 1'b0;
parameter cfg_rx0_pcs_m_comma_val_i = 10'b0000000000;
parameter cfg_rx0_pcs_nb_comma_bef_realign_i = 2'b00;
parameter cfg_rx0_pcs_p_comma_en_i = 1'b0;
parameter cfg_rx0_pcs_p_comma_val_i = 10'b0000000000;
parameter cfg_rx0_pcs_polarity_i = 1'b0;
parameter cfg_rx0_pcs_protocol_size_i = 1'b0;
parameter cfg_rx0_pcs_replace_bypass_i = 1'b0;
parameter cfg_rx0_pcs_sync_supported_i = 1'b0;
parameter cfg_rx0_pma_cdr_cp_i = 4'b0000;
parameter cfg_rx0_pma_clk_pos_i = 1'b0;
parameter cfg_rx0_pma_coarse_ppm_i = 3'b000;
parameter cfg_rx0_pma_ctrl_term_i = 6'b000000;
parameter cfg_rx0_pma_dco_divl_i = 2'b00;
parameter cfg_rx0_pma_dco_divm_i = 1'b0;
parameter cfg_rx0_pma_dco_divn_i = 2'b00;
parameter cfg_rx0_pma_dco_reg_res_i = 2'b00;
parameter cfg_rx0_pma_dco_vref_sel_i = 1'b0;
parameter cfg_rx0_pma_fine_ppm_i = 3'b000;
parameter cfg_rx0_pma_loopback_i = 1'b0;
parameter cfg_rx0_pma_m_eye_ppm_i = 3'b000;
parameter cfg_rx0_pma_peak_detect_cmd_i = 2'b00;
parameter cfg_rx0_pma_peak_detect_on_i = 1'b0;
parameter cfg_rx0_pma_pll_cpump_n_i = 3'b000;
parameter cfg_rx0_pma_pll_divf_en_n_i = 1'b0;
parameter cfg_rx0_pma_pll_divf_i = 2'b00;
parameter cfg_rx0_pma_pll_divm_en_n_i = 1'b0;
parameter cfg_rx0_pma_pll_divm_i = 2'b00;
parameter cfg_rx0_pma_pll_divn_en_n_i = 1'b0;
parameter cfg_rx0_pma_pll_divn_i = 1'b0;
parameter cfg_rx1_gearbox_en_i = 1'b0;
parameter cfg_rx1_gearbox_mode_i = 1'b0;
parameter cfg_rx1_pcs_8b_dscr_sel_i = 1'b0;
parameter cfg_rx1_pcs_align_bypass_i = 1'b0;
parameter cfg_rx1_pcs_buffers_bypass_i = 1'b0;
parameter cfg_rx1_pcs_buffers_use_cdc_i = 1'b0;
parameter cfg_rx1_pcs_bypass_pma_cdc_i = 1'b0;
parameter cfg_rx1_pcs_bypass_usr_cdc_i = 1'b0;
parameter cfg_rx1_pcs_comma_mask_i = 10'b0000000000;
parameter cfg_rx1_pcs_debug_en_i = 1'b0;
parameter cfg_rx1_pcs_dec_bypass_i = 1'b0;
parameter cfg_rx1_pcs_dscr_bypass_i = 1'b0;
parameter cfg_rx1_pcs_el_buff_diff_bef_comp_i = 4'b0000;
parameter cfg_rx1_pcs_el_buff_max_comp_i = 4'b0000;
parameter cfg_rx1_pcs_el_buff_only_one_skp_i = 1'b0;
parameter cfg_rx1_pcs_el_buff_skp_char_0_i = 9'b000000000;
parameter cfg_rx1_pcs_el_buff_skp_char_1_i = 9'b000000000;
parameter cfg_rx1_pcs_el_buff_skp_char_2_i = 9'b000000000;
parameter cfg_rx1_pcs_el_buff_skp_char_3_i = 9'b000000000;
parameter cfg_rx1_pcs_el_buff_skp_header_0_i = 9'b000000000;
parameter cfg_rx1_pcs_el_buff_skp_header_1_i = 9'b000000000;
parameter cfg_rx1_pcs_el_buff_skp_header_2_i = 9'b000000000;
parameter cfg_rx1_pcs_el_buff_skp_header_3_i = 9'b000000000;
parameter cfg_rx1_pcs_el_buff_skp_header_size_i = 2'b00;
parameter cfg_rx1_pcs_el_buff_skp_seq_size_i = 2'b00;
parameter cfg_rx1_pcs_fsm_sel_i = 2'b00;
parameter cfg_rx1_pcs_fsm_watchdog_en_i = 1'b0;
parameter cfg_rx1_pcs_loopback_i = 1'b0;
parameter cfg_rx1_pcs_m_comma_en_i = 1'b0;
parameter cfg_rx1_pcs_m_comma_val_i = 10'b0000000000;
parameter cfg_rx1_pcs_nb_comma_bef_realign_i = 2'b00;
parameter cfg_rx1_pcs_p_comma_en_i = 1'b0;
parameter cfg_rx1_pcs_p_comma_val_i = 10'b0000000000;
parameter cfg_rx1_pcs_polarity_i = 1'b0;
parameter cfg_rx1_pcs_protocol_size_i = 1'b0;
parameter cfg_rx1_pcs_replace_bypass_i = 1'b0;
parameter cfg_rx1_pcs_sync_supported_i = 1'b0;
parameter cfg_rx1_pma_cdr_cp_i = 4'b0000;
parameter cfg_rx1_pma_clk_pos_i = 1'b0;
parameter cfg_rx1_pma_coarse_ppm_i = 3'b000;
parameter cfg_rx1_pma_ctrl_term_i = 6'b000000;
parameter cfg_rx1_pma_dco_divl_i = 2'b00;
parameter cfg_rx1_pma_dco_divm_i = 1'b0;
parameter cfg_rx1_pma_dco_divn_i = 2'b00;
parameter cfg_rx1_pma_dco_reg_res_i = 2'b00;
parameter cfg_rx1_pma_dco_vref_sel_i = 1'b0;
parameter cfg_rx1_pma_fine_ppm_i = 3'b000;
parameter cfg_rx1_pma_loopback_i = 1'b0;
parameter cfg_rx1_pma_m_eye_ppm_i = 3'b000;
parameter cfg_rx1_pma_peak_detect_cmd_i = 2'b00;
parameter cfg_rx1_pma_peak_detect_on_i = 1'b0;
parameter cfg_rx1_pma_pll_cpump_n_i = 3'b000;
parameter cfg_rx1_pma_pll_divf_en_n_i = 1'b0;
parameter cfg_rx1_pma_pll_divf_i = 2'b00;
parameter cfg_rx1_pma_pll_divm_en_n_i = 1'b0;
parameter cfg_rx1_pma_pll_divm_i = 2'b00;
parameter cfg_rx1_pma_pll_divn_en_n_i = 1'b0;
parameter cfg_rx1_pma_pll_divn_i = 1'b0;
parameter cfg_rx2_gearbox_en_i = 1'b0;
parameter cfg_rx2_gearbox_mode_i = 1'b0;
parameter cfg_rx2_pcs_8b_dscr_sel_i = 1'b0;
parameter cfg_rx2_pcs_align_bypass_i = 1'b0;
parameter cfg_rx2_pcs_buffers_bypass_i = 1'b0;
parameter cfg_rx2_pcs_buffers_use_cdc_i = 1'b0;
parameter cfg_rx2_pcs_bypass_pma_cdc_i = 1'b0;
parameter cfg_rx2_pcs_bypass_usr_cdc_i = 1'b0;
parameter cfg_rx2_pcs_comma_mask_i = 10'b0000000000;
parameter cfg_rx2_pcs_debug_en_i = 1'b0;
parameter cfg_rx2_pcs_dec_bypass_i = 1'b0;
parameter cfg_rx2_pcs_dscr_bypass_i = 1'b0;
parameter cfg_rx2_pcs_el_buff_diff_bef_comp_i = 4'b0000;
parameter cfg_rx2_pcs_el_buff_max_comp_i = 4'b0000;
parameter cfg_rx2_pcs_el_buff_only_one_skp_i = 1'b0;
parameter cfg_rx2_pcs_el_buff_skp_char_0_i = 9'b000000000;
parameter cfg_rx2_pcs_el_buff_skp_char_1_i = 9'b000000000;
parameter cfg_rx2_pcs_el_buff_skp_char_2_i = 9'b000000000;
parameter cfg_rx2_pcs_el_buff_skp_char_3_i = 9'b000000000;
parameter cfg_rx2_pcs_el_buff_skp_header_0_i = 9'b000000000;
parameter cfg_rx2_pcs_el_buff_skp_header_1_i = 9'b000000000;
parameter cfg_rx2_pcs_el_buff_skp_header_2_i = 9'b000000000;
parameter cfg_rx2_pcs_el_buff_skp_header_3_i = 9'b000000000;
parameter cfg_rx2_pcs_el_buff_skp_header_size_i = 2'b00;
parameter cfg_rx2_pcs_el_buff_skp_seq_size_i = 2'b00;
parameter cfg_rx2_pcs_fsm_sel_i = 2'b00;
parameter cfg_rx2_pcs_fsm_watchdog_en_i = 1'b0;
parameter cfg_rx2_pcs_loopback_i = 1'b0;
parameter cfg_rx2_pcs_m_comma_en_i = 1'b0;
parameter cfg_rx2_pcs_m_comma_val_i = 10'b0000000000;
parameter cfg_rx2_pcs_nb_comma_bef_realign_i = 2'b00;
parameter cfg_rx2_pcs_p_comma_en_i = 1'b0;
parameter cfg_rx2_pcs_p_comma_val_i = 10'b0000000000;
parameter cfg_rx2_pcs_polarity_i = 1'b0;
parameter cfg_rx2_pcs_protocol_size_i = 1'b0;
parameter cfg_rx2_pcs_replace_bypass_i = 1'b0;
parameter cfg_rx2_pcs_sync_supported_i = 1'b0;
parameter cfg_rx2_pma_cdr_cp_i = 4'b0000;
parameter cfg_rx2_pma_clk_pos_i = 1'b0;
parameter cfg_rx2_pma_coarse_ppm_i = 3'b000;
parameter cfg_rx2_pma_ctrl_term_i = 6'b000000;
parameter cfg_rx2_pma_dco_divl_i = 2'b00;
parameter cfg_rx2_pma_dco_divm_i = 1'b0;
parameter cfg_rx2_pma_dco_divn_i = 2'b00;
parameter cfg_rx2_pma_dco_reg_res_i = 2'b00;
parameter cfg_rx2_pma_dco_vref_sel_i = 1'b0;
parameter cfg_rx2_pma_fine_ppm_i = 3'b000;
parameter cfg_rx2_pma_loopback_i = 1'b0;
parameter cfg_rx2_pma_m_eye_ppm_i = 3'b000;
parameter cfg_rx2_pma_peak_detect_cmd_i = 2'b00;
parameter cfg_rx2_pma_peak_detect_on_i = 1'b0;
parameter cfg_rx2_pma_pll_cpump_n_i = 3'b000;
parameter cfg_rx2_pma_pll_divf_en_n_i = 1'b0;
parameter cfg_rx2_pma_pll_divf_i = 2'b00;
parameter cfg_rx2_pma_pll_divm_en_n_i = 1'b0;
parameter cfg_rx2_pma_pll_divm_i = 2'b00;
parameter cfg_rx2_pma_pll_divn_en_n_i = 1'b0;
parameter cfg_rx2_pma_pll_divn_i = 1'b0;
parameter cfg_rx3_gearbox_en_i = 1'b0;
parameter cfg_rx3_gearbox_mode_i = 1'b0;
parameter cfg_rx3_pcs_8b_dscr_sel_i = 1'b0;
parameter cfg_rx3_pcs_align_bypass_i = 1'b0;
parameter cfg_rx3_pcs_buffers_bypass_i = 1'b0;
parameter cfg_rx3_pcs_buffers_use_cdc_i = 1'b0;
parameter cfg_rx3_pcs_bypass_pma_cdc_i = 1'b0;
parameter cfg_rx3_pcs_bypass_usr_cdc_i = 1'b0;
parameter cfg_rx3_pcs_comma_mask_i = 10'b0000000000;
parameter cfg_rx3_pcs_debug_en_i = 1'b0;
parameter cfg_rx3_pcs_dec_bypass_i = 1'b0;
parameter cfg_rx3_pcs_dscr_bypass_i = 1'b0;
parameter cfg_rx3_pcs_el_buff_diff_bef_comp_i = 4'b0000;
parameter cfg_rx3_pcs_el_buff_max_comp_i = 4'b0000;
parameter cfg_rx3_pcs_el_buff_only_one_skp_i = 1'b0;
parameter cfg_rx3_pcs_el_buff_skp_char_0_i = 9'b000000000;
parameter cfg_rx3_pcs_el_buff_skp_char_1_i = 9'b000000000;
parameter cfg_rx3_pcs_el_buff_skp_char_2_i = 9'b000000000;
parameter cfg_rx3_pcs_el_buff_skp_char_3_i = 9'b000000000;
parameter cfg_rx3_pcs_el_buff_skp_header_0_i = 9'b000000000;
parameter cfg_rx3_pcs_el_buff_skp_header_1_i = 9'b000000000;
parameter cfg_rx3_pcs_el_buff_skp_header_2_i = 9'b000000000;
parameter cfg_rx3_pcs_el_buff_skp_header_3_i = 9'b000000000;
parameter cfg_rx3_pcs_el_buff_skp_header_size_i = 2'b00;
parameter cfg_rx3_pcs_el_buff_skp_seq_size_i = 2'b00;
parameter cfg_rx3_pcs_fsm_sel_i = 2'b00;
parameter cfg_rx3_pcs_fsm_watchdog_en_i = 1'b0;
parameter cfg_rx3_pcs_loopback_i = 1'b0;
parameter cfg_rx3_pcs_m_comma_en_i = 1'b0;
parameter cfg_rx3_pcs_m_comma_val_i = 10'b0000000000;
parameter cfg_rx3_pcs_nb_comma_bef_realign_i = 2'b00;
parameter cfg_rx3_pcs_p_comma_en_i = 1'b0;
parameter cfg_rx3_pcs_p_comma_val_i = 10'b0000000000;
parameter cfg_rx3_pcs_polarity_i = 1'b0;
parameter cfg_rx3_pcs_protocol_size_i = 1'b0;
parameter cfg_rx3_pcs_replace_bypass_i = 1'b0;
parameter cfg_rx3_pcs_sync_supported_i = 1'b0;
parameter cfg_rx3_pma_cdr_cp_i = 4'b0000;
parameter cfg_rx3_pma_clk_pos_i = 1'b0;
parameter cfg_rx3_pma_coarse_ppm_i = 3'b000;
parameter cfg_rx3_pma_ctrl_term_i = 6'b000000;
parameter cfg_rx3_pma_dco_divl_i = 2'b00;
parameter cfg_rx3_pma_dco_divm_i = 1'b0;
parameter cfg_rx3_pma_dco_divn_i = 2'b00;
parameter cfg_rx3_pma_dco_reg_res_i = 2'b00;
parameter cfg_rx3_pma_dco_vref_sel_i = 1'b0;
parameter cfg_rx3_pma_fine_ppm_i = 3'b000;
parameter cfg_rx3_pma_loopback_i = 1'b0;
parameter cfg_rx3_pma_m_eye_ppm_i = 3'b000;
parameter cfg_rx3_pma_peak_detect_cmd_i = 2'b00;
parameter cfg_rx3_pma_peak_detect_on_i = 1'b0;
parameter cfg_rx3_pma_pll_cpump_n_i = 3'b000;
parameter cfg_rx3_pma_pll_divf_en_n_i = 1'b0;
parameter cfg_rx3_pma_pll_divf_i = 2'b00;
parameter cfg_rx3_pma_pll_divm_en_n_i = 1'b0;
parameter cfg_rx3_pma_pll_divm_i = 2'b00;
parameter cfg_rx3_pma_pll_divn_en_n_i = 1'b0;
parameter cfg_rx3_pma_pll_divn_i = 1'b0;
parameter cfg_test_mode_i = 2'b00;
parameter cfg_tx0_gearbox_en_i = 1'b0;
parameter cfg_tx0_gearbox_mode_i = 1'b0;
parameter cfg_tx0_pcs_8b_scr_sel_i = 1'b0;
parameter cfg_tx0_pcs_bypass_pma_cdc_i = 1'b0;
parameter cfg_tx0_pcs_bypass_usr_cdc_i = 1'b0;
parameter cfg_tx0_pcs_enc_bypass_i = 1'b0;
parameter cfg_tx0_pcs_esistream_fsm_en_i = 1'b0;
parameter cfg_tx0_pcs_loopback_i = 1'b0;
parameter cfg_tx0_pcs_polarity_i = 1'b0;
parameter cfg_tx0_pcs_protocol_size_i = 1'b0;
parameter cfg_tx0_pcs_replace_bypass_i = 1'b0;
parameter cfg_tx0_pcs_scr_bypass_i = 1'b0;
parameter cfg_tx0_pcs_scr_init_i = 17'b00000000000000000;
parameter cfg_tx0_pcs_sync_supported_i = 1'b0;
parameter cfg_tx0_pma_clk_pos_i = 1'b0;
parameter cfg_tx0_pma_loopback_i = 1'b0;
parameter cfg_tx1_gearbox_en_i = 1'b0;
parameter cfg_tx1_gearbox_mode_i = 1'b0;
parameter cfg_tx1_pcs_8b_scr_sel_i = 1'b0;
parameter cfg_tx1_pcs_bypass_pma_cdc_i = 1'b0;
parameter cfg_tx1_pcs_bypass_usr_cdc_i = 1'b0;
parameter cfg_tx1_pcs_enc_bypass_i = 1'b0;
parameter cfg_tx1_pcs_esistream_fsm_en_i = 1'b0;
parameter cfg_tx1_pcs_loopback_i = 1'b0;
parameter cfg_tx1_pcs_polarity_i = 1'b0;
parameter cfg_tx1_pcs_protocol_size_i = 1'b0;
parameter cfg_tx1_pcs_replace_bypass_i = 1'b0;
parameter cfg_tx1_pcs_scr_bypass_i = 1'b0;
parameter cfg_tx1_pcs_scr_init_i = 17'b00000000000000000;
parameter cfg_tx1_pcs_sync_supported_i = 1'b0;
parameter cfg_tx1_pma_clk_pos_i = 1'b0;
parameter cfg_tx1_pma_loopback_i = 1'b0;
parameter cfg_tx2_gearbox_en_i = 1'b0;
parameter cfg_tx2_gearbox_mode_i = 1'b0;
parameter cfg_tx2_pcs_8b_scr_sel_i = 1'b0;
parameter cfg_tx2_pcs_bypass_pma_cdc_i = 1'b0;
parameter cfg_tx2_pcs_bypass_usr_cdc_i = 1'b0;
parameter cfg_tx2_pcs_enc_bypass_i = 1'b0;
parameter cfg_tx2_pcs_esistream_fsm_en_i = 1'b0;
parameter cfg_tx2_pcs_loopback_i = 1'b0;
parameter cfg_tx2_pcs_polarity_i = 1'b0;
parameter cfg_tx2_pcs_protocol_size_i = 1'b0;
parameter cfg_tx2_pcs_replace_bypass_i = 1'b0;
parameter cfg_tx2_pcs_scr_bypass_i = 1'b0;
parameter cfg_tx2_pcs_scr_init_i = 17'b00000000000000000;
parameter cfg_tx2_pcs_sync_supported_i = 1'b0;
parameter cfg_tx2_pma_clk_pos_i = 1'b0;
parameter cfg_tx2_pma_loopback_i = 1'b0;
parameter cfg_tx3_gearbox_en_i = 1'b0;
parameter cfg_tx3_gearbox_mode_i = 1'b0;
parameter cfg_tx3_pcs_8b_scr_sel_i = 1'b0;
parameter cfg_tx3_pcs_bypass_pma_cdc_i = 1'b0;
parameter cfg_tx3_pcs_bypass_usr_cdc_i = 1'b0;
parameter cfg_tx3_pcs_enc_bypass_i = 1'b0;
parameter cfg_tx3_pcs_esistream_fsm_en_i = 1'b0;
parameter cfg_tx3_pcs_loopback_i = 1'b0;
parameter cfg_tx3_pcs_polarity_i = 1'b0;
parameter cfg_tx3_pcs_protocol_size_i = 1'b0;
parameter cfg_tx3_pcs_replace_bypass_i = 1'b0;
parameter cfg_tx3_pcs_scr_bypass_i = 1'b0;
parameter cfg_tx3_pcs_scr_init_i = 17'b00000000000000000;
parameter cfg_tx3_pcs_sync_supported_i = 1'b0;
parameter cfg_tx3_pma_clk_pos_i = 1'b0;
parameter cfg_tx3_pma_loopback_i = 1'b0;
parameter location = "";
parameter rx_usrclk_use_pcs_clk_2 = 1'b0;
parameter tx_usrclk_use_pcs_clk_2 = 1'b0;
endmodule