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This commit is contained in:
Miodrag Milanovic 2024-03-13 10:57:58 +01:00
parent 71f0984dc9
commit b202126c76
7 changed files with 2118 additions and 1833 deletions
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302
techlibs/nanoxplore/cells_wrap_l.v
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@ -1401,7 +1401,7 @@ module NX_RFB(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13,
);
endmodule
// TODO
//TODO
module SMUL24x32_2DSP_ACC_2DSP_L(clk, rst, we, A, B, Z);
input [23:0] A;
input [31:0] B;
@ -1411,3 +1411,303 @@ module SMUL24x32_2DSP_ACC_2DSP_L(clk, rst, we, A, B, Z);
input we;
endmodule
//TODO
module NX_HSSL_L_FULL(hssl_clk_user_i, hssl_clk_ref_i, hssl_clock_o, usr_com_tx_pma_pre_sign_i, usr_com_tx_pma_pre_en_i, usr_com_tx_pma_main_sign_i, usr_com_rx_pma_m_eye_i, usr_com_tx_pma_post_sign_i, usr_pll_pma_rst_n_i, usr_main_rst_n_i, usr_calibrate_pma_en_i, usr_pcs_ctrl_pll_lock_en_i, usr_pcs_ctrl_ovs_en_i, usr_pll_lock_o, usr_calibrate_pma_out_o, pma_clk_ext_i, usr_tx0_ctrl_replace_en_i, usr_tx0_rst_n_i, usr_tx0_pma_clk_en_i, usr_tx0_busy_o, pma_tx0_o
, usr_rx0_ctrl_dscr_en_i, usr_rx0_ctrl_dec_en_i, usr_rx0_ctrl_align_en_i, usr_rx0_ctrl_align_sync_i, usr_rx0_ctrl_replace_en_i, usr_rx0_ctrl_el_buff_rst_i, usr_rx0_ctrl_el_buff_fifo_en_i, usr_rx0_rst_n_i, usr_rx0_pma_cdr_rst_i, usr_rx0_pma_ckgen_rst_n_i, usr_rx0_pma_pll_rst_n_i, usr_rx0_pma_loss_of_signal_o, usr_rx0_ctrl_char_is_aligned_o, usr_rx0_busy_o, usr_rx0_pll_lock_o, pma_rx0_i, usr_tx1_ctrl_replace_en_i, usr_tx1_rst_n_i, usr_tx1_pma_clk_en_i, usr_tx1_busy_o, pma_tx1_o
, usr_rx1_ctrl_dscr_en_i, usr_rx1_ctrl_dec_en_i, usr_rx1_ctrl_align_en_i, usr_rx1_ctrl_align_sync_i, usr_rx1_ctrl_replace_en_i, usr_rx1_ctrl_el_buff_rst_i, usr_rx1_ctrl_el_buff_fifo_en_i, usr_rx1_rst_n_i, usr_rx1_pma_cdr_rst_i, usr_rx1_pma_ckgen_rst_n_i, usr_rx1_pma_pll_rst_n_i, usr_rx1_pma_loss_of_signal_o, usr_rx1_ctrl_char_is_aligned_o, usr_rx1_busy_o, usr_rx1_pll_lock_o, pma_rx1_i, usr_tx2_ctrl_replace_en_i, usr_tx2_rst_n_i, usr_tx2_pma_clk_en_i, usr_tx2_busy_o, pma_tx2_o
, usr_rx2_ctrl_dscr_en_i, usr_rx2_ctrl_dec_en_i, usr_rx2_ctrl_align_en_i, usr_rx2_ctrl_align_sync_i, usr_rx2_ctrl_replace_en_i, usr_rx2_ctrl_el_buff_rst_i, usr_rx2_ctrl_el_buff_fifo_en_i, usr_rx2_rst_n_i, usr_rx2_pma_cdr_rst_i, usr_rx2_pma_ckgen_rst_n_i, usr_rx2_pma_pll_rst_n_i, usr_rx2_pma_loss_of_signal_o, usr_rx2_ctrl_char_is_aligned_o, usr_rx2_busy_o, usr_rx2_pll_lock_o, pma_rx2_i, usr_tx3_ctrl_replace_en_i, usr_tx3_rst_n_i, usr_tx3_pma_clk_en_i, usr_tx3_busy_o, pma_tx3_o
, usr_rx3_ctrl_dscr_en_i, usr_rx3_ctrl_dec_en_i, usr_rx3_ctrl_align_en_i, usr_rx3_ctrl_align_sync_i, usr_rx3_ctrl_replace_en_i, usr_rx3_ctrl_el_buff_rst_i, usr_rx3_ctrl_el_buff_fifo_en_i, usr_rx3_rst_n_i, usr_rx3_pma_cdr_rst_i, usr_rx3_pma_ckgen_rst_n_i, usr_rx3_pma_pll_rst_n_i, usr_rx3_pma_loss_of_signal_o, usr_rx3_ctrl_char_is_aligned_o, usr_rx3_busy_o, usr_rx3_pll_lock_o, pma_rx3_i, usr_tx4_ctrl_replace_en_i, usr_tx4_rst_n_i, usr_tx4_pma_clk_en_i, usr_tx4_busy_o, pma_tx4_o
, usr_rx4_ctrl_dscr_en_i, usr_rx4_ctrl_dec_en_i, usr_rx4_ctrl_align_en_i, usr_rx4_ctrl_align_sync_i, usr_rx4_ctrl_replace_en_i, usr_rx4_ctrl_el_buff_rst_i, usr_rx4_ctrl_el_buff_fifo_en_i, usr_rx4_rst_n_i, usr_rx4_pma_cdr_rst_i, usr_rx4_pma_ckgen_rst_n_i, usr_rx4_pma_pll_rst_n_i, usr_rx4_pma_loss_of_signal_o, usr_rx4_ctrl_char_is_aligned_o, usr_rx4_busy_o, usr_rx4_pll_lock_o, pma_rx4_i, usr_tx5_ctrl_replace_en_i, usr_tx5_rst_n_i, usr_tx5_pma_clk_en_i, usr_tx5_busy_o, pma_tx5_o
, usr_rx5_ctrl_dscr_en_i, usr_rx5_ctrl_dec_en_i, usr_rx5_ctrl_align_en_i, usr_rx5_ctrl_align_sync_i, usr_rx5_ctrl_replace_en_i, usr_rx5_ctrl_el_buff_rst_i, usr_rx5_ctrl_el_buff_fifo_en_i, usr_rx5_rst_n_i, usr_rx5_pma_cdr_rst_i, usr_rx5_pma_ckgen_rst_n_i, usr_rx5_pma_pll_rst_n_i, usr_rx5_pma_loss_of_signal_o, usr_rx5_ctrl_char_is_aligned_o, usr_rx5_busy_o, usr_rx5_pll_lock_o, pma_rx5_i, usr_com_tx_pma_main_en_i, usr_com_tx_pma_margin_sel_i, usr_com_tx_pma_margin_input_sel_i, usr_com_tx_pma_margin_sel_var_i, usr_com_tx_pma_margin_input_sel_var_i
, usr_com_tx_pma_post_en_i, usr_com_tx_pma_post_input_sel_i, usr_com_tx_pma_post_input_sel_var_i, usr_com_rx_pma_ctle_cap_i, usr_com_rx_pma_ctle_resp_i, usr_com_rx_pma_ctle_resn_i, usr_com_ctrl_tx_sel_i, usr_com_ctrl_rx_sel_i, usr_calibrate_pma_res_p1_i, usr_calibrate_pma_res_n2_i, usr_calibrate_pma_res_n3_i, usr_calibrate_pma_res_p4_i, usr_calibrate_pma_sel_i, usr_main_test_i, usr_main_test_o, usr_tx0_ctrl_enc_en_i, usr_tx0_ctrl_char_is_k_i, usr_tx0_ctrl_scr_en_i, usr_tx0_ctrl_end_of_multiframe_i, usr_tx0_ctrl_end_of_frame_i, usr_tx0_test_i
, usr_tx0_data_i, usr_tx0_test_o, usr_rx0_data_o, usr_rx0_ctrl_ovs_bit_sel_i, usr_rx0_test_i, usr_rx0_ctrl_char_is_comma_o, usr_rx0_ctrl_char_is_k_o, usr_rx0_ctrl_not_in_table_o, usr_rx0_ctrl_disp_err_o, usr_rx0_ctrl_char_is_a_o, usr_rx0_ctrl_char_is_f_o, usr_rx0_test_o, usr_tx1_ctrl_enc_en_i, usr_tx1_ctrl_char_is_k_i, usr_tx1_ctrl_scr_en_i, usr_tx1_ctrl_end_of_multiframe_i, usr_tx1_ctrl_end_of_frame_i, usr_tx1_test_i, usr_tx1_data_i, usr_tx1_test_o, usr_rx1_data_o
, usr_rx1_ctrl_ovs_bit_sel_i, usr_rx1_test_i, usr_rx1_ctrl_char_is_comma_o, usr_rx1_ctrl_char_is_k_o, usr_rx1_ctrl_not_in_table_o, usr_rx1_ctrl_disp_err_o, usr_rx1_ctrl_char_is_a_o, usr_rx1_ctrl_char_is_f_o, usr_rx1_test_o, usr_tx2_ctrl_enc_en_i, usr_tx2_ctrl_char_is_k_i, usr_tx2_ctrl_scr_en_i, usr_tx2_ctrl_end_of_multiframe_i, usr_tx2_ctrl_end_of_frame_i, usr_tx2_test_i, usr_tx2_data_i, usr_tx2_test_o, usr_rx2_data_o, usr_rx2_ctrl_ovs_bit_sel_i, usr_rx2_test_i, usr_rx2_ctrl_char_is_comma_o
, usr_rx2_ctrl_char_is_k_o, usr_rx2_ctrl_not_in_table_o, usr_rx2_ctrl_disp_err_o, usr_rx2_ctrl_char_is_a_o, usr_rx2_ctrl_char_is_f_o, usr_rx2_test_o, usr_tx3_ctrl_enc_en_i, usr_tx3_ctrl_char_is_k_i, usr_tx3_ctrl_scr_en_i, usr_tx3_ctrl_end_of_multiframe_i, usr_tx3_ctrl_end_of_frame_i, usr_tx3_test_i, usr_tx3_data_i, usr_tx3_test_o, usr_rx3_data_o, usr_rx3_ctrl_ovs_bit_sel_i, usr_rx3_test_i, usr_rx3_ctrl_char_is_comma_o, usr_rx3_ctrl_char_is_k_o, usr_rx3_ctrl_not_in_table_o, usr_rx3_ctrl_disp_err_o
, usr_rx3_ctrl_char_is_a_o, usr_rx3_ctrl_char_is_f_o, usr_rx3_test_o, usr_tx4_ctrl_enc_en_i, usr_tx4_ctrl_char_is_k_i, usr_tx4_ctrl_scr_en_i, usr_tx4_ctrl_end_of_multiframe_i, usr_tx4_ctrl_end_of_frame_i, usr_tx4_test_i, usr_tx4_data_i, usr_tx4_test_o, usr_rx4_data_o, usr_rx4_ctrl_ovs_bit_sel_i, usr_rx4_test_i, usr_rx4_ctrl_char_is_comma_o, usr_rx4_ctrl_char_is_k_o, usr_rx4_ctrl_not_in_table_o, usr_rx4_ctrl_disp_err_o, usr_rx4_ctrl_char_is_a_o, usr_rx4_ctrl_char_is_f_o, usr_rx4_test_o
, usr_tx5_ctrl_enc_en_i, usr_tx5_ctrl_char_is_k_i, usr_tx5_ctrl_scr_en_i, usr_tx5_ctrl_end_of_multiframe_i, usr_tx5_ctrl_end_of_frame_i, usr_tx5_test_i, usr_tx5_data_i, usr_tx5_test_o, usr_rx5_data_o, usr_rx5_ctrl_ovs_bit_sel_i, usr_rx5_test_i, usr_rx5_ctrl_char_is_comma_o, usr_rx5_ctrl_char_is_k_o, usr_rx5_ctrl_not_in_table_o, usr_rx5_ctrl_disp_err_o, usr_rx5_ctrl_char_is_a_o, usr_rx5_ctrl_char_is_f_o, usr_rx5_test_o, usr_com_tx_pma_pre_input_sel_i);
input hssl_clk_ref_i;
input hssl_clk_user_i;
output hssl_clock_o;
input pma_clk_ext_i;
input pma_rx0_i;
input pma_rx1_i;
input pma_rx2_i;
input pma_rx3_i;
input pma_rx4_i;
input pma_rx5_i;
output pma_tx0_o;
output pma_tx1_o;
output pma_tx2_o;
output pma_tx3_o;
output pma_tx4_o;
output pma_tx5_o;
input usr_calibrate_pma_en_i;
output usr_calibrate_pma_out_o;
input [7:0] usr_calibrate_pma_res_n2_i;
input [7:0] usr_calibrate_pma_res_n3_i;
input [7:0] usr_calibrate_pma_res_p1_i;
input [7:0] usr_calibrate_pma_res_p4_i;
input [3:0] usr_calibrate_pma_sel_i;
input [5:0] usr_com_ctrl_rx_sel_i;
input [5:0] usr_com_ctrl_tx_sel_i;
input [3:0] usr_com_rx_pma_ctle_cap_i;
input [3:0] usr_com_rx_pma_ctle_resn_i;
input [3:0] usr_com_rx_pma_ctle_resp_i;
input usr_com_rx_pma_m_eye_i;
input [5:0] usr_com_tx_pma_main_en_i;
input usr_com_tx_pma_main_sign_i;
input [3:0] usr_com_tx_pma_margin_input_sel_i;
input [4:0] usr_com_tx_pma_margin_input_sel_var_i;
input [3:0] usr_com_tx_pma_margin_sel_i;
input [4:0] usr_com_tx_pma_margin_sel_var_i;
input [4:0] usr_com_tx_pma_post_en_i;
input [3:0] usr_com_tx_pma_post_input_sel_i;
input [3:0] usr_com_tx_pma_post_input_sel_var_i;
input usr_com_tx_pma_post_sign_i;
input usr_com_tx_pma_pre_en_i;
input [3:0] usr_com_tx_pma_pre_input_sel_i;
input usr_com_tx_pma_pre_sign_i;
input usr_main_rst_n_i;
input [7:0] usr_main_test_i;
output [7:0] usr_main_test_o;
input usr_pcs_ctrl_ovs_en_i;
input usr_pcs_ctrl_pll_lock_en_i;
output usr_pll_lock_o;
input usr_pll_pma_rst_n_i;
output usr_rx0_busy_o;
input usr_rx0_ctrl_align_en_i;
input usr_rx0_ctrl_align_sync_i;
output [7:0] usr_rx0_ctrl_char_is_a_o;
output usr_rx0_ctrl_char_is_aligned_o;
output [7:0] usr_rx0_ctrl_char_is_comma_o;
output [7:0] usr_rx0_ctrl_char_is_f_o;
output [7:0] usr_rx0_ctrl_char_is_k_o;
input usr_rx0_ctrl_dec_en_i;
output [7:0] usr_rx0_ctrl_disp_err_o;
input usr_rx0_ctrl_dscr_en_i;
input usr_rx0_ctrl_el_buff_fifo_en_i;
input usr_rx0_ctrl_el_buff_rst_i;
output [7:0] usr_rx0_ctrl_not_in_table_o;
input [1:0] usr_rx0_ctrl_ovs_bit_sel_i;
input usr_rx0_ctrl_replace_en_i;
output [63:0] usr_rx0_data_o;
output usr_rx0_pll_lock_o;
input usr_rx0_pma_cdr_rst_i;
input usr_rx0_pma_ckgen_rst_n_i;
output usr_rx0_pma_loss_of_signal_o;
input usr_rx0_pma_pll_rst_n_i;
input usr_rx0_rst_n_i;
input [3:0] usr_rx0_test_i;
output [7:0] usr_rx0_test_o;
output usr_rx1_busy_o;
input usr_rx1_ctrl_align_en_i;
input usr_rx1_ctrl_align_sync_i;
output [7:0] usr_rx1_ctrl_char_is_a_o;
output usr_rx1_ctrl_char_is_aligned_o;
output [7:0] usr_rx1_ctrl_char_is_comma_o;
output [7:0] usr_rx1_ctrl_char_is_f_o;
output [7:0] usr_rx1_ctrl_char_is_k_o;
input usr_rx1_ctrl_dec_en_i;
output [7:0] usr_rx1_ctrl_disp_err_o;
input usr_rx1_ctrl_dscr_en_i;
input usr_rx1_ctrl_el_buff_fifo_en_i;
input usr_rx1_ctrl_el_buff_rst_i;
output [7:0] usr_rx1_ctrl_not_in_table_o;
input [1:0] usr_rx1_ctrl_ovs_bit_sel_i;
input usr_rx1_ctrl_replace_en_i;
output [63:0] usr_rx1_data_o;
output usr_rx1_pll_lock_o;
input usr_rx1_pma_cdr_rst_i;
input usr_rx1_pma_ckgen_rst_n_i;
output usr_rx1_pma_loss_of_signal_o;
input usr_rx1_pma_pll_rst_n_i;
input usr_rx1_rst_n_i;
input [3:0] usr_rx1_test_i;
output [7:0] usr_rx1_test_o;
output usr_rx2_busy_o;
input usr_rx2_ctrl_align_en_i;
input usr_rx2_ctrl_align_sync_i;
output [7:0] usr_rx2_ctrl_char_is_a_o;
output usr_rx2_ctrl_char_is_aligned_o;
output [7:0] usr_rx2_ctrl_char_is_comma_o;
output [7:0] usr_rx2_ctrl_char_is_f_o;
output [7:0] usr_rx2_ctrl_char_is_k_o;
input usr_rx2_ctrl_dec_en_i;
output [7:0] usr_rx2_ctrl_disp_err_o;
input usr_rx2_ctrl_dscr_en_i;
input usr_rx2_ctrl_el_buff_fifo_en_i;
input usr_rx2_ctrl_el_buff_rst_i;
output [7:0] usr_rx2_ctrl_not_in_table_o;
input [1:0] usr_rx2_ctrl_ovs_bit_sel_i;
input usr_rx2_ctrl_replace_en_i;
output [63:0] usr_rx2_data_o;
output usr_rx2_pll_lock_o;
input usr_rx2_pma_cdr_rst_i;
input usr_rx2_pma_ckgen_rst_n_i;
output usr_rx2_pma_loss_of_signal_o;
input usr_rx2_pma_pll_rst_n_i;
input usr_rx2_rst_n_i;
input [3:0] usr_rx2_test_i;
output [7:0] usr_rx2_test_o;
output usr_rx3_busy_o;
input usr_rx3_ctrl_align_en_i;
input usr_rx3_ctrl_align_sync_i;
output [7:0] usr_rx3_ctrl_char_is_a_o;
output usr_rx3_ctrl_char_is_aligned_o;
output [7:0] usr_rx3_ctrl_char_is_comma_o;
output [7:0] usr_rx3_ctrl_char_is_f_o;
output [7:0] usr_rx3_ctrl_char_is_k_o;
input usr_rx3_ctrl_dec_en_i;
output [7:0] usr_rx3_ctrl_disp_err_o;
input usr_rx3_ctrl_dscr_en_i;
input usr_rx3_ctrl_el_buff_fifo_en_i;
input usr_rx3_ctrl_el_buff_rst_i;
output [7:0] usr_rx3_ctrl_not_in_table_o;
input [1:0] usr_rx3_ctrl_ovs_bit_sel_i;
input usr_rx3_ctrl_replace_en_i;
output [63:0] usr_rx3_data_o;
output usr_rx3_pll_lock_o;
input usr_rx3_pma_cdr_rst_i;
input usr_rx3_pma_ckgen_rst_n_i;
output usr_rx3_pma_loss_of_signal_o;
input usr_rx3_pma_pll_rst_n_i;
input usr_rx3_rst_n_i;
input [3:0] usr_rx3_test_i;
output [7:0] usr_rx3_test_o;
output usr_rx4_busy_o;
input usr_rx4_ctrl_align_en_i;
input usr_rx4_ctrl_align_sync_i;
output [7:0] usr_rx4_ctrl_char_is_a_o;
output usr_rx4_ctrl_char_is_aligned_o;
output [7:0] usr_rx4_ctrl_char_is_comma_o;
output [7:0] usr_rx4_ctrl_char_is_f_o;
output [7:0] usr_rx4_ctrl_char_is_k_o;
input usr_rx4_ctrl_dec_en_i;
output [7:0] usr_rx4_ctrl_disp_err_o;
input usr_rx4_ctrl_dscr_en_i;
input usr_rx4_ctrl_el_buff_fifo_en_i;
input usr_rx4_ctrl_el_buff_rst_i;
output [7:0] usr_rx4_ctrl_not_in_table_o;
input [1:0] usr_rx4_ctrl_ovs_bit_sel_i;
input usr_rx4_ctrl_replace_en_i;
output [63:0] usr_rx4_data_o;
output usr_rx4_pll_lock_o;
input usr_rx4_pma_cdr_rst_i;
input usr_rx4_pma_ckgen_rst_n_i;
output usr_rx4_pma_loss_of_signal_o;
input usr_rx4_pma_pll_rst_n_i;
input usr_rx4_rst_n_i;
input [3:0] usr_rx4_test_i;
output [7:0] usr_rx4_test_o;
output usr_rx5_busy_o;
input usr_rx5_ctrl_align_en_i;
input usr_rx5_ctrl_align_sync_i;
output [7:0] usr_rx5_ctrl_char_is_a_o;
output usr_rx5_ctrl_char_is_aligned_o;
output [7:0] usr_rx5_ctrl_char_is_comma_o;
output [7:0] usr_rx5_ctrl_char_is_f_o;
output [7:0] usr_rx5_ctrl_char_is_k_o;
input usr_rx5_ctrl_dec_en_i;
output [7:0] usr_rx5_ctrl_disp_err_o;
input usr_rx5_ctrl_dscr_en_i;
input usr_rx5_ctrl_el_buff_fifo_en_i;
input usr_rx5_ctrl_el_buff_rst_i;
output [7:0] usr_rx5_ctrl_not_in_table_o;
input [1:0] usr_rx5_ctrl_ovs_bit_sel_i;
input usr_rx5_ctrl_replace_en_i;
output [63:0] usr_rx5_data_o;
output usr_rx5_pll_lock_o;
input usr_rx5_pma_cdr_rst_i;
input usr_rx5_pma_ckgen_rst_n_i;
output usr_rx5_pma_loss_of_signal_o;
input usr_rx5_pma_pll_rst_n_i;
input usr_rx5_rst_n_i;
input [3:0] usr_rx5_test_i;
output [7:0] usr_rx5_test_o;
output usr_tx0_busy_o;
input [7:0] usr_tx0_ctrl_char_is_k_i;
input [7:0] usr_tx0_ctrl_enc_en_i;
input [7:0] usr_tx0_ctrl_end_of_frame_i;
input [7:0] usr_tx0_ctrl_end_of_multiframe_i;
input usr_tx0_ctrl_replace_en_i;
input [7:0] usr_tx0_ctrl_scr_en_i;
input [63:0] usr_tx0_data_i;
input usr_tx0_pma_clk_en_i;
input usr_tx0_rst_n_i;
input [3:0] usr_tx0_test_i;
output [3:0] usr_tx0_test_o;
output usr_tx1_busy_o;
input [7:0] usr_tx1_ctrl_char_is_k_i;
input [7:0] usr_tx1_ctrl_enc_en_i;
input [7:0] usr_tx1_ctrl_end_of_frame_i;
input [7:0] usr_tx1_ctrl_end_of_multiframe_i;
input usr_tx1_ctrl_replace_en_i;
input [7:0] usr_tx1_ctrl_scr_en_i;
input [63:0] usr_tx1_data_i;
input usr_tx1_pma_clk_en_i;
input usr_tx1_rst_n_i;
input [3:0] usr_tx1_test_i;
output [3:0] usr_tx1_test_o;
output usr_tx2_busy_o;
input [7:0] usr_tx2_ctrl_char_is_k_i;
input [7:0] usr_tx2_ctrl_enc_en_i;
input [7:0] usr_tx2_ctrl_end_of_frame_i;
input [7:0] usr_tx2_ctrl_end_of_multiframe_i;
input usr_tx2_ctrl_replace_en_i;
input [7:0] usr_tx2_ctrl_scr_en_i;
input [63:0] usr_tx2_data_i;
input usr_tx2_pma_clk_en_i;
input usr_tx2_rst_n_i;
input [3:0] usr_tx2_test_i;
output [3:0] usr_tx2_test_o;
output usr_tx3_busy_o;
input [7:0] usr_tx3_ctrl_char_is_k_i;
input [7:0] usr_tx3_ctrl_enc_en_i;
input [7:0] usr_tx3_ctrl_end_of_frame_i;
input [7:0] usr_tx3_ctrl_end_of_multiframe_i;
input usr_tx3_ctrl_replace_en_i;
input [7:0] usr_tx3_ctrl_scr_en_i;
input [63:0] usr_tx3_data_i;
input usr_tx3_pma_clk_en_i;
input usr_tx3_rst_n_i;
input [3:0] usr_tx3_test_i;
output [3:0] usr_tx3_test_o;
output usr_tx4_busy_o;
input [7:0] usr_tx4_ctrl_char_is_k_i;
input [7:0] usr_tx4_ctrl_enc_en_i;
input [7:0] usr_tx4_ctrl_end_of_frame_i;
input [7:0] usr_tx4_ctrl_end_of_multiframe_i;
input usr_tx4_ctrl_replace_en_i;
input [7:0] usr_tx4_ctrl_scr_en_i;
input [63:0] usr_tx4_data_i;
input usr_tx4_pma_clk_en_i;
input usr_tx4_rst_n_i;
input [3:0] usr_tx4_test_i;
output [3:0] usr_tx4_test_o;
output usr_tx5_busy_o;
input [7:0] usr_tx5_ctrl_char_is_k_i;
input [7:0] usr_tx5_ctrl_enc_en_i;
input [7:0] usr_tx5_ctrl_end_of_frame_i;
input [7:0] usr_tx5_ctrl_end_of_multiframe_i;
input usr_tx5_ctrl_replace_en_i;
input [7:0] usr_tx5_ctrl_scr_en_i;
input [63:0] usr_tx5_data_i;
input usr_tx5_pma_clk_en_i;
input usr_tx5_rst_n_i;
input [3:0] usr_tx5_test_i;
output [3:0] usr_tx5_test_o;
parameter cfg_main_i = 34'b0000000000000000000000000000000000;
parameter cfg_rx0_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter cfg_rx1_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter cfg_rx2_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter cfg_rx3_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter cfg_rx4_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter cfg_rx5_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter cfg_tx0_i = 0;
parameter cfg_tx1_i = 0;
parameter cfg_tx2_i = 0;
parameter cfg_tx3_i = 0;
parameter cfg_tx4_i = 0;
parameter cfg_tx5_i = 0;
parameter location = "";
endmodule