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Miodrag Milanovic 2024-03-13 10:57:58 +01:00
parent 71f0984dc9
commit b202126c76
7 changed files with 2118 additions and 1833 deletions

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@ -2001,3 +2001,156 @@ module NX_RFB_L(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13
parameter rck_edge = 1'b0;
parameter wck_edge = 1'b0;
endmodule
(* blackbox *)
module NX_IOM_CONTROL_L(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1, C2RW2, C2RW3
, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DC, CCK, DCK, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3
, DRA4, DRA5, DRA6, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1
, CAP2, CAP3, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1, DRO2, DRO3, DRO4
, DRO5, DRO6, CAL, LINK2, LINK3, LINK4, LINK5, LINK6, LINK7, LINK8, LINK9, LINK10, LINK11, LINK12, LINK13, LINK14, LINK15, LINK16, LINK17, LINK18, LINK19
, LINK20, LINK21, LINK22, LINK23, LINK24, LINK25, LINK26, LINK27, LINK28, LINK29, LINK30, LINK31, LINK32, LINK33, LINK34, LINK1);
output C1RED;
input C1RNE;
input C1RS;
input C1RW1;
input C1RW2;
input C1RW3;
input C1TS;
input C1TW;
output C2RED;
input C2RNE;
input C2RS;
input C2RW1;
input C2RW2;
input C2RW3;
input C2TS;
input C2TW;
input CAD1;
input CAD2;
input CAD3;
input CAD4;
input CAD5;
input CAD6;
output CAL;
input CAN1;
input CAN2;
input CAN3;
input CAN4;
input CAP1;
input CAP2;
input CAP3;
input CAP4;
input CAT1;
input CAT2;
input CAT3;
input CAT4;
input CCK;
output CKO1;
output CKO2;
input CTCK;
input DC;
input DCK;
input DIG;
input DIS;
input DOG;
input DOS;
input DPAG;
input DPAS;
input DQSG;
input DQSS;
input DRA1;
input DRA2;
input DRA3;
input DRA4;
input DRA5;
input DRA6;
input DRI1;
input DRI2;
input DRI3;
input DRI4;
input DRI5;
input DRI6;
input DRL;
output DRO1;
output DRO2;
output DRO3;
output DRO4;
output DRO5;
output DRO6;
input DS1;
input DS2;
input FA1;
input FA2;
input FA3;
input FA4;
input FA5;
input FA6;
output FLD;
output FLG;
input FZ;
inout [41:0] LINK1;
inout [41:0] LINK10;
inout [41:0] LINK11;
inout [41:0] LINK12;
inout [41:0] LINK13;
inout [41:0] LINK14;
inout [41:0] LINK15;
inout [41:0] LINK16;
inout [41:0] LINK17;
inout [41:0] LINK18;
inout [41:0] LINK19;
inout [41:0] LINK2;
inout [41:0] LINK20;
inout [41:0] LINK21;
inout [41:0] LINK22;
inout [41:0] LINK23;
inout [41:0] LINK24;
inout [41:0] LINK25;
inout [41:0] LINK26;
inout [41:0] LINK27;
inout [41:0] LINK28;
inout [41:0] LINK29;
inout [41:0] LINK3;
inout [41:0] LINK30;
inout [41:0] LINK31;
inout [41:0] LINK32;
inout [41:0] LINK33;
inout [41:0] LINK34;
inout [41:0] LINK4;
inout [41:0] LINK5;
inout [41:0] LINK6;
inout [41:0] LINK7;
inout [41:0] LINK8;
inout [41:0] LINK9;
input RRCK1;
input RRCK2;
input RTCK1;
input RTCK2;
input WRCK1;
input WRCK2;
input WTCK1;
input WTCK2;
parameter div_rx1 = 4'b0000;
parameter div_rx2 = 4'b0000;
parameter div_tx1 = 4'b0000;
parameter div_tx2 = 4'b0000;
parameter inv_di_fclk1 = 1'b0;
parameter inv_di_fclk2 = 1'b0;
parameter latency1 = 1'b0;
parameter latency2 = 1'b0;
parameter location = "";
parameter mode_cpath = "";
parameter mode_epath = "";
parameter mode_io_cal = 1'b0;
parameter mode_rpath = "";
parameter mode_side1 = 0;
parameter mode_side2 = 0;
parameter mode_tpath = "";
parameter sel_clk_out1 = 1'b0;
parameter sel_clk_out2 = 1'b0;
parameter sel_clkr_rx1 = 1'b0;
parameter sel_clkr_rx2 = 1'b0;
parameter sel_clkw_rx1 = 2'b00;
parameter sel_clkw_rx2 = 2'b00;
endmodule