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Added "design -reset-vlog"

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This commit is contained in:
Clifford Wolf 2016-11-30 11:25:55 +01:00
parent ac7a175a3c
commit b1cdf772eb
1 changed files with 32 additions and 7 deletions
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39
passes/cmds/design.cc
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@ -17,10 +17,8 @@
* *
*/ */
#include "kernel/register.h" #include "kernel/yosys.h"
#include "kernel/celltypes.h" #include "frontends/ast/ast.h"
#include "kernel/rtlil.h"
#include "kernel/log.h"
YOSYS_NAMESPACE_BEGIN YOSYS_NAMESPACE_BEGIN
@ -82,11 +80,18 @@ struct DesignPass : public Pass {
log("\n"); log("\n");
log("Copy modules from the current design into the specified one.\n"); log("Copy modules from the current design into the specified one.\n");
log("\n"); log("\n");
log("\n");
log(" design -reset-vlog\n");
log("\n");
log("The Verilog front-end remembers defined macros and top-level declarations\n");
log("between calls to 'read_verilog'. This command resets this memory.\n");
log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{ {
bool got_mode = false; bool got_mode = false;
bool reset_mode = false; bool reset_mode = false;
bool reset_vlog_mode = false;
bool push_mode = false; bool push_mode = false;
bool pop_mode = false; bool pop_mode = false;
RTLIL::Design *copy_from_design = NULL, *copy_to_design = NULL; RTLIL::Design *copy_from_design = NULL, *copy_to_design = NULL;
@ -102,6 +107,11 @@ struct DesignPass : public Pass {
reset_mode = true; reset_mode = true;
continue; continue;
} }
if (!got_mode && args[argidx] == "-reset-vlog") {
got_mode = true;
reset_vlog_mode = true;
continue;
}
if (!got_mode && args[argidx] == "-push") { if (!got_mode && args[argidx] == "-push") {
got_mode = true; got_mode = true;
push_mode = true; push_mode = true;
@ -235,19 +245,34 @@ struct DesignPass : public Pass {
design->selection_stack.push_back(RTLIL::Selection()); design->selection_stack.push_back(RTLIL::Selection());
} }
if (reset_mode || reset_vlog_mode || !load_name.empty() || push_mode || pop_mode)
{
for (auto node : design->verilog_packages)
delete node;
design->verilog_packages.clear();
for (auto node : design->verilog_globals)
delete node;
design->verilog_globals.clear();
design->verilog_defines.clear();
}
if (!load_name.empty() || pop_mode) if (!load_name.empty() || pop_mode)
{ {
RTLIL::Design *saved_design = pop_mode ? pushed_designs.back() : saved_designs.at(load_name); RTLIL::Design *saved_design = pop_mode ? pushed_designs.back() : saved_designs.at(load_name);
if (pop_mode)
pushed_designs.pop_back();
for (auto &it : saved_design->modules_) for (auto &it : saved_design->modules_)
design->add(it.second->clone()); design->add(it.second->clone());
design->selection_stack = saved_design->selection_stack; design->selection_stack = saved_design->selection_stack;
design->selection_vars = saved_design->selection_vars; design->selection_vars = saved_design->selection_vars;
design->selected_active_module = saved_design->selected_active_module; design->selected_active_module = saved_design->selected_active_module;
if (pop_mode) {
delete saved_design;
pushed_designs.pop_back();
}
} }
} }
} DesignPass; } DesignPass;