mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-17 04:50:29 +00:00
analogdevices: LUTRAM config
This commit is contained in:
parent
763c69b554
commit
b1bc39bca4
4 changed files with 191 additions and 2544 deletions
|
@ -1,19 +1,14 @@
|
|||
# LUT RAMs for Virtex 5, Virtex 6, Spartan 6, Series 7.
|
||||
# The corresponding mapping file is lutrams_xc5v_map.v
|
||||
|
||||
# Single-port RAMs.
|
||||
|
||||
ram distributed $__ANALOGDEVICES_LUTRAM_SP_ {
|
||||
cost 8;
|
||||
widthscale;
|
||||
cost 1;
|
||||
option "ABITS" 5 {
|
||||
abits 5;
|
||||
widths 8 global;
|
||||
}
|
||||
option "ABITS" 6 {
|
||||
abits 6;
|
||||
widths 4 global;
|
||||
}
|
||||
width 1;
|
||||
init no_undef;
|
||||
prune_rom;
|
||||
port arsw "RW" {
|
||||
|
@ -24,47 +19,19 @@ ram distributed $__ANALOGDEVICES_LUTRAM_SP_ {
|
|||
# Dual-port RAMs.
|
||||
|
||||
ram distributed $__ANALOGDEVICES_LUTRAM_DP_ {
|
||||
cost 8;
|
||||
widthscale;
|
||||
cost 1;
|
||||
option "ABITS" 5 {
|
||||
abits 5;
|
||||
widths 4 global;
|
||||
}
|
||||
option "ABITS" 6 {
|
||||
abits 6;
|
||||
widths 2 global;
|
||||
}
|
||||
option "ABITS" 7 {
|
||||
abits 7;
|
||||
widths 1 global;
|
||||
}
|
||||
width 1;
|
||||
init no_undef;
|
||||
prune_rom;
|
||||
port ar "R" {
|
||||
}
|
||||
port arsw "RW" {
|
||||
clock posedge;
|
||||
}
|
||||
port ar "R" {
|
||||
}
|
||||
}
|
||||
|
||||
# Simple dual port RAMs.
|
||||
|
||||
ram distributed $__ANALOGDEVICES_LUTRAM_SDP_ {
|
||||
cost 8;
|
||||
widthscale 7;
|
||||
option "ABITS" 5 {
|
||||
abits 5;
|
||||
widths 6 global;
|
||||
}
|
||||
option "ABITS" 6 {
|
||||
abits 6;
|
||||
widths 3 global;
|
||||
}
|
||||
init no_undef;
|
||||
prune_rom;
|
||||
port sw "W" {
|
||||
clock posedge;
|
||||
}
|
||||
port ar "R" {
|
||||
}
|
||||
}
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue